Patents by Inventor Marcel Kossel
Marcel Kossel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160358635Abstract: The invention relates to a receiving unit for performing a calibration of a reference voltage, comprising a reference voltage unit for generating and applying a reference voltage on the evaluation unit depending on a converter value, an evaluation unit for receiving a single-ended data signal and being configured to determine an evaluation signal based on the data signal and the reference voltage, and a logic unit configured to perform a calibration process for calibrating the reference voltage. The logic unit is configured to command a memory device to apply a permanent digital logical state on a data line, to iteratively adapt a converter voltage to substantially match the voltage level of the logical state on the data line, and to determine the reference voltage depending on the converter voltage for which the voltage level of the logical state on the data line has been substantially matched.Type: ApplicationFiled: June 3, 2015Publication date: December 8, 2016Inventors: Matthias Braendli, Marcel A. Kossel
-
MULTIPLY-AND-ACCUMULATE UNIT IN CARRY-SAVE ADDER FORMAT AND APPLICATION IN A FEEDBACK LOOP EQUALIZER
Publication number: 20160342393Abstract: The invention relates to a multiply and accumulation (MAC) unit for multiplying a provided first and a provided second multiplicand and for adding a provided summand to the resulting product. The MAC includes at least one multiplication block which is configured to multiply the first multiplicand and the second multiplicand, wherein the first multiplicand is given in a carry-save adder format, wherein the multiplication result is provided in a carry-save format, and a carry-save adder which is configured to add to the result of the multiplication the provided summand.Type: ApplicationFiled: May 18, 2016Publication date: November 24, 2016Inventor: Marcel Kossel -
Patent number: 9496008Abstract: The invention relates to a receiving unit for performing a calibration of a reference voltage, comprising a reference voltage unit for generating and applying a reference voltage on the evaluation unit depending on a converter value, an evaluation unit for receiving a single-ended data signal and being configured to determine an evaluation signal based on the data signal and the reference voltage, and a logic unit configured to perform a calibration process for calibrating the reference voltage. The logic unit is configured to command a memory device to apply a permanent digital logical state on a data line, to iteratively adapt a converter voltage to substantially match the voltage level of the logical state on the data line, and to determine the reference voltage depending on the converter voltage for which the voltage level of the logical state on the data line has been substantially matched.Type: GrantFiled: June 3, 2015Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Matthias Braendli, Marcel A. Kossel
-
Publication number: 20160322938Abstract: The invention relates to a multi-phase oscillator for generating multiple phase-shifted oscillator signals including: a ring oscillator having a number of concatenated oscillator delay cells which are interconnected to generate an oscillator signal, wherein phase-shifted oscillator signals are generated between the oscillator delay cells; a phase-blending unit configured to receive two phase-shifted oscillator signals and to generate a mid-phase oscillator signal whose phase shift is between the shifts of the two phase-shifted oscillator signals; and an interpolator delay line having a number of concatenated interpolator delay cells to generate further phase-shifted oscillator signals.Type: ApplicationFiled: July 13, 2016Publication date: November 3, 2016Applicant: International Business Machines CorporationInventors: Marcel A Kossel, Daihyun Lim, Pradeep Thiagarajan
-
Publication number: 20160173069Abstract: The invention relates to a multi-phase oscillator for generating multiple phase-shifted oscillator signals including: a ring oscillator having a number of concatenated oscillator delay cells which are interconnected to generate an oscillator signal, wherein phase-shifted oscillator signals are generated between the oscillator delay cells; a phase-blending unit configured to receive two phase-shifted oscillator signals and to generate a mid-phase oscillator signal whose phase shift is between the shifts of the two phase-shifted oscillator signals; and an interpolator delay line having a number of concatenated interpolator delay cells to generate further phase-shifted oscillator signals.Type: ApplicationFiled: December 15, 2015Publication date: June 16, 2016Inventors: Marcel A. Kossel, Daihyun Lim, Pradeep Thiagarajan
-
Publication number: 20160087822Abstract: The present invention relates to a method for generating multi-level PRBS patterns for testing purposes, wherein the method includes the steps of providing a binary PRBS signal with a binary bit pattern sequence and mapping each bit of the binary bit pattern sequence to a symbol of a multilevel output.Type: ApplicationFiled: September 24, 2015Publication date: March 24, 2016Inventor: Marcel A. Kossel
-
Publication number: 20160056809Abstract: A method and system for reducing leakage current in a testing circuit are provided. Embodiments include a testing circuit that includes a digital buffer that includes a first transistor operatively coupled to a second transistor, where a drain of the first transistor is operatively coupled to a source of the second transistor. The second transistor is switched into cutoff mode. The digital buffer also includes a reference voltage generation circuit. The reference voltage generation circuit is operatively connected to the drain of the first transistor and the source of the second transistor. The reference voltage generation circuit is configured to reduce the leakage current in the digital buffer.Type: ApplicationFiled: August 21, 2014Publication date: February 25, 2016Inventors: SARVESWARA BADE, SHIU CHUNG HO, MARCEL A. KOSSEL, PRADEEP THIAGARAJAN
-
Patent number: 9020021Abstract: An apparatus for encoding data signals includes a transmitter configured to encode and transmit a data signal over a communication channel, the transmitter including a precoder; a signal shaper configured to adjust the data signal by applying an equalization setting to the data signal, the equalization setting including an amplitude and offset and transmit the adjusted data signal to the precoder; and a processing unit. The processing unit is configured to perform: receiving channel coefficients associated with the communication channel; for each of a plurality of amplitude settings and a plurality of offset settings, calculating whether a modulo amplitude level would occur at a receiver using a modulo operation; selecting the equalization setting from the plurality of amplitude settings and the plurality of offset settings based on the calculation; and transmitting a control signal specifying the equalization setting to the signal shaper.Type: GrantFiled: July 29, 2013Date of Patent: April 28, 2015Assignee: International Business Machines CorporationInventors: Marcel A. Kossel, Daihyun Lim, Pradeep Thiagarajan
-
Patent number: 9009520Abstract: A slew rate controller for a computing system includes a slew rate control module, the slew rate control module further comprising a plurality of sampling modules, each sampling module corresponding to one of a plurality of phase signal inputs, wherein each sampling module receives an input signal, a reference voltage, and the sampling module's respective phase signal input, and wherein each sampling module generates a respective sample of a relationship between the input signal and the reference voltage during a time period indicated by the sampling module's respective phase signal input; and a finite state machine configured to output a slew rate control signal to control a slew rate of the input signal based on the plurality of samples from the sampling modules.Type: GrantFiled: August 29, 2011Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Marcel A. Kossel, Daihyun Lim, Pradeep Thiagarajan
-
Patent number: 8981831Abstract: A method and circuit for implementing a level shifter with built-in-logic function for reduced delay. The circuit including at least one set of inputs from a first power supply domain. The circuit further including at least two cross coupled field effect transistors (FETs) connected to a second power supply domain. The circuit further including a true logic gate connected to the first power supply domain and the at least two cross coupled FETs. The true logic gate being configured to generate a logic function based on the at least one set of inputs. The circuit further including a complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs. The complementary logic gate being configured to generate a complement of the logic function based on the at least one set of inputs.Type: GrantFiled: September 11, 2013Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Marcel A. Kossel, Daihyun Lim, Pradeep Thiagarajan
-
Publication number: 20150070069Abstract: A method and circuit for implementing a level shifter with built-in-logic function for reduced delay. The circuit including at least one set of inputs from a first power supply domain. The circuit further including at least two cross coupled field effect transistors (FETs) connected to a second power supply domain. The circuit further including a true logic gate connected to the first power supply domain and the at least two cross coupled FETs. The true logic gate being configured to generate a logic function based on the at least one set of inputs. The circuit further including a complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs. The complementary logic gate being configured to generate a complement of the logic function based on the at least one set of inputs.Type: ApplicationFiled: September 11, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: Marcel A. KOSSEL, Daihyun LIM, Pradeep THIAGARAJAN
-
Publication number: 20150030062Abstract: An apparatus for encoding data signals includes a transmitter configured to encode and transmit a data signal over a communication channel, the transmitter including a precoder; a signal shaper configured to adjust the data signal by applying an equalization setting to the data signal, the equalization setting including an amplitude and offset and transmit the adjusted data signal to the precoder; and a processing unit. The processing unit is configured to perform: receiving channel coefficients associated with the communication channel; for each of a plurality of amplitude settings and a plurality of offset settings, calculating whether a modulo amplitude level would occur at a receiver using a modulo operation; selecting the equalization setting from the plurality of amplitude settings and the plurality of offset settings based on the calculation; and transmitting a control signal specifying the equalization setting to the signal shaper.Type: ApplicationFiled: July 29, 2013Publication date: January 29, 2015Applicant: International Business Machines CorporationInventors: Marcel A. Kossel, Daihyun Lim, Pradeep Thiagarajan
-
Patent number: 8717138Abstract: An inductor including a primary coil coaxially arranged and operated in parallel with isolated secondary coils each including at least one loop winding with two open-circuited ports. At least one phase shifting device is arranged between open-circuited ports of at least one secondary coil. A method to operate an inductor by combining primary and secondary coils with phase shifting devices to get a wide tuning range is also provided. The method includes the step of phase shifting open-circuited ports of at least one secondary coil.Type: GrantFiled: July 25, 2012Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: Marcel A. Kossel, Thomas E. Morf, Martin Leo Schmatz, Jonas R. Weiss
-
Patent number: 8692600Abstract: Multi-protocol driver slew rate calibration systems for calibrating slew rate control signal values are provided. Embodiments include generating, by a first phase rotator, a first clock signal; generating, by the second phase rotator, a second clock signal; initially setting, by a calibration controller, phase selector amounts such that the first clock signal is delayed relative to the second clock signal; determining whether the first clock signal is delayed relative to the second clock signal; if the first clock signal is delayed, changing the second phase selector amount; and if the first clock signal is not delayed, using the first clock signal and the second clock signal to calibrate values of control signals provided to control a slew rate of a calibration clock delay line such that the slew rate of the calibration clock delay line substantially matches a target slew rate.Type: GrantFiled: January 9, 2013Date of Patent: April 8, 2014Assignee: International Business Machines CorporationInventors: Rafael Blanco, Marcel A. Kossel, Michael A. Sorna
-
Patent number: 8686776Abstract: A phase rotator based on voltage referencing is disclosed. A voltage signal is generated that is proportional to the phase difference between two input signals. The voltage signal is then used as the upper voltage limit for a digital-to-analog converter (DAC). The DAC is programmable via an input vector to generate a DAC output. The DAC output is used to generate a phase rotated (phase shifted) output, which is at an intermediate phase between the two input signals.Type: GrantFiled: July 24, 2012Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Daihyun Lim, Marcel A. Kossel, Pradeep Thiagarajan
-
Patent number: 8674737Abstract: A slew rate control circuit configured to control a slew rate of driver circuit comprises a clock delay module that receives a half-rate clock signal and that includes a plurality of delay cells configured to generate a plurality of respective delayed clock signals each having a different time delay from one another. A driver module includes a plurality of multiplexers in electrical communication with a respective data cell to receive a corresponding delayed clock signal. The multiplexers are configured to output a respective full-rate data stream in response to the delayed clock signal. The slew driver module further includes an output stage circuit in electrical communication with each multiplexer to combine each full-rate data stream and to generate a final step-wise driving signal that controls the slew rate.Type: GrantFiled: September 7, 2012Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Marcel A. Kossel, Michael A. Sorna, Thomas H. Toifl, Glen A. Wiedemeier
-
Publication number: 20140070864Abstract: A slew rate control circuit configured to control a slew rate of driver circuit comprises a clock delay module that receives a half-rate clock signal and that includes a plurality of delay cells configured to generate a plurality of respective delayed clock signals each having a different time delay from one another. A driver module includes a plurality of multiplexers in electrical communication with a respective data cell to receive a corresponding delayed clock signal. The multiplexers are configured to output a respective full-rate data stream in response to the delayed clock signal. The slew driver module further includes an output stage circuit in electrical communication with each multiplexer to combine each full-rate data stream and to generate a final step-wise driving signal that controls the slew rate.Type: ApplicationFiled: September 7, 2012Publication date: March 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marcel A. Kossel, Michael A. Sorna, Thomas H. Toifl, Glen A. Wiedemeier
-
Publication number: 20140035643Abstract: Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer.Type: ApplicationFiled: August 6, 2012Publication date: February 6, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marcel A. Kossel, Daihyun Lim, Pradeep Thiagarajan
-
Publication number: 20140028363Abstract: A phase rotator based on voltage referencing is disclosed. A voltage signal is generated that is proportional to the phase difference between two input signals. The voltage signal is then used as the upper voltage limit for a digital-to-analog converter (DAC). The DAC is programmable via an input vector to generate a DAC output. The DAC output is used to generate a phase rotated (phase shifted) output, which is at an intermediate phase between the two input signals.Type: ApplicationFiled: July 24, 2012Publication date: January 30, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daihyun Lim, Marcel A. Kossel, Pradeep Thiagarajan
-
Patent number: 8638149Abstract: Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer.Type: GrantFiled: August 6, 2012Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Marcel A. Kossel, Daihyun Lim, Pradeep Thiagarajan