Abstract: A method for sending data to a memory chip includes receiving data at a data transmitter disposed on a memory hub chip, applying Tomlinson-Harashima precoding (THP) equalization to the data prior to transmitting the data; and transmitting the data from the transmitter to a memory chip.

Abstract: A slew rate control circuit generates a slew-rate controlled clock signal from an input clock signal based on a feedback control mechanism. The feedback control mechanism uses the input clock signal duty cycle characteristics as a reference for controlling and maintaining an optimum slew rate for the slew-rate controlled clock signal. By using the input clock signal as a reference, the slew-rate controlled clock signal is dynamically measured and periodically adjusted over each cycle of the input clock signal.

Abstract: A method for startup and operation of an output stage of a transmitter, the output stage comprising a first protection field effect transistor (FET) and a second protection FET includes enabling a startup circuit; providing a first bias voltage to the first protection FET in the output stage and a second bias voltage to the second protection FET stage in the output stage by the startup circuit; disabling the startup circuit and enabling a protection voltage generator; providing the first bias voltage to the first protection FET in the output stage by the protection voltage generator; and providing the second bias voltage to the second protection FET in the output stage by a second bias voltage power supply.

Abstract: A method for startup and operation of an output stage of a transmitter, the output stage comprising a first protection field effect transistor (FET) and a second protection FET includes enabling a startup circuit; providing a first bias voltage to the first protection FET in the output stage and a second bias voltage to the second protection FET stage in the output stage by the startup circuit; disabling the startup circuit and enabling a protection voltage generator; providing the first bias voltage to the first protection FET in the output stage by the protection voltage generator; and providing the second bias voltage to the second protection FET in the output stage by a second bias voltage power supply.

Abstract: A system includes a memory hub chip including a Tomlinson-Harashima precoding (THP) equalizer portion operative to perform transmitter equalization at the memory hub chip and send data from to a memory chip.

Abstract: An inductor including a primary coil coaxially arranged and operated in parallel with isolated secondary coils each including at least one loop winding with two open-circuited ports. At least one phase shifting device is arranged between open-circuited ports of at least one secondary coil. A method to operate an inductor by combining primary and secondary coils with phase shifting devices to get a wide tuning range is also provided. The method includes the step of phase shifting open-circuited ports of at least one secondary coil.

Abstract: A slew rate controller for a computing system includes a slew rate control module, the slew rate control module further comprising a plurality of sampling modules, each sampling module corresponding to one of a plurality of phase signal inputs, wherein each sampling module receives an input signal, a reference voltage, and the sampling module's respective phase signal input, and wherein each sampling module generates a respective sample of a relationship between the input signal and the reference voltage during a time period indicated by the sampling module's respective phase signal input; and a finite state machine configured to output a slew rate control signal to control a slew rate of the input signal based on the plurality of samples from the sampling modules.

Abstract: An inductor including a primary coil coaxially arranged and operated in parallel with isolated secondary coils each including at least one loop winding with two open-circuited ports. At least one phase shifting device is arranged between open-circuited ports of at least one secondary coil. A method to operate an inductor by combining primary and secondary coils with phase shifting devices to get a wide tuning range is also provided. The method includes the step of phase shifting open-circuited ports of at least one secondary coil.

Abstract: A method for sending data to a memory chip includes receiving data at a data transmitter disposed on a memory hub chip, applying Tomlinson-Harashima precoding (THP) equalization to the data prior to transmitting the data; and transmitting the data from the transmitter to a memory chip.

Abstract: A system includes a memory hub chip including a Tomlinson-Harashima precoding (THP) equalizer portion operative to perform transmitter equalization at the memory hub chip and send data from to a memory chip.

Abstract: A phase rotator includes a phase selector stage operative to receive a clock signal and output a first phase and a second phase of the clock signal, a slew rate control stage including a first pass gate circuit operative to control a slew rate of the first phase of the clock signal and a second pass gate circuit operative to control a slew rate of the second phase of the clock signal, and a phase blending stage operative to combine the first phase with the second phase of the clock signal and output a phase rotated signal.

Abstract: A phase rotator includes a phase selector stage operative to receive a clock signal and output a first phase and a second phase of the clock signal, a slew rate control stage including a first pass gate circuit operative to control a slew rate of the first phase of the clock signal and a second pass gate circuit operative to control a slew rate of the second phase of the clock signal, and a phase blending stage operative to combine the first phase with the second phase of the clock signal and output a phase rotated signal.

Abstract: A continuously tunable inductor with an inductive-capacitive (LC) voltage controlled oscillator (VCO) having a primary coil. The inductor includes a separate isolated secondary coil, a set of transistors composing a closed loop with the secondary coil, a magnetic coupling between the primary coil of the LC VCO and the secondary coil, an electrical coupling between the LC VCO and the set of transistors composing a closed loop with the secondary coil, and means for electric current injection into the closed loop. Such an inductor can be tuned by modulating a mutual inductance, which is magnetically and electrically coupled with the LC VCO by injection of an electric current (I0).

Abstract: An inductor and method of operating the inductor by combining primary and secondary coils with passive coupling, active parallel, or active cross-coupling structures. The first includes at least one passive coupling structure having at least one coupling coil arranged between a primary coil and at least one of the secondary coils and/or between two of the secondary coils. The second includes an active coupling structure arranged between a primary coil and at least one secondary coil and/or between at least two of the secondary coils, to selectively parallel couple the primary coil and one of the secondary coils and/or at least two of the secondary coils. The third includes an active coupling structure to selectively cross couple a primary coil and at least one of the secondary coils and/or to selectively cross couple at least two of the secondary coils.

Abstract: A digital-to-analog (DAC) converter that includes a plurality of dynamically operated slave digital-to-analog (DAC) converters, each having a switched current mirror and a storage capacitor, and a static master digital-to-analog (DAC) converter in communication with the plurality of dynamically operated slave DAC converters, that distributes a current to at least one of the plurality of slave DAC converters such that voltage across the storage capacitor of the at least one slave DAC converter controls the switch current mirror so that the at least one slave DAC converter outputs currents that are equivalent to digital codes applied to the static master DAC converter. A ring counter is used to periodically refresh the charges on the storage capacitors that are lost by leakage. In addition to the periodic updates, an end user may perform immediate updates of selected slave DACs if necessary, via the ring counter.

Abstract: A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.

Abstract: A signal generator device for generating at least one periodic signal for use in a data eye scan system. The signal generator comprises a clock input, at least one output and at least one signal generator coupled with the clock input and with the output. The signal generator is at least one token ring with a predetermined number of positions and is operable to propagate at least one token in the ring by moving the token from its current position to a following position dependent on a clock signal from the clock input. The signal generator further comprises a predetermined number of signal value units that each represent a respective predetermined signal value of a predetermined signal waveform and are operable to provide the signal value at an output of the signal generator dependent on a current position of the at least one token in the token ring.

Abstract: A method, apparatus, and system for a data synchronizer/serial link receiver that performs the alignment of the sampling clock used to retime asynchronous customer data by the application of a negative delay onto the system clock whereas the value of the applied negative delay is derived from the analysis of a temperature code obtained by a tapped delay line in conjunction with the application of preceding replica delay lines for the in-phase and quadrature clock signals.

Abstract: A system and apparatus for varactor bank switching for a voltage controlled oscillator, is disclosed. Varactor bank switching involves partitioning a varactor bank switch into two anti-parallel branches, wherein each branch comprises a pass-gate circuit that is series-connected to a fixed varactor or capacitor; and maintaining an output common mode voltage of an actual oscillator signal at the varactor-side terminal of each pass-gate circuit, such that a threshold voltage of the switch transistor in the pass-gate circuit is not exceeded and the switch remains in an off-state.

Abstract: A method and apparatus for varactor bank switching for a voltage controlled oscillator is disclosed. Varactor bank switching involves generating a negative bias voltage signal as a control signal for a varactor bank switch in an off-state, the varactor bank switch comprising a pass-gate circuit including switching transistors. Generating the negative bias voltage signal includes employing an active rectifier circuit running at the speed of an oscillation signal, the negative bias voltage signal maintaining the gate-source voltage of the pass-gate circuit below a threshold voltage to prevent said switching transistors from becoming conductive in an off-state.