Abstract: The present invention provides an apparatus and method for operating driver amplifier (20) of a line driver circuit (10) from a lower set of power supply voltages, and from a higher set of voltages only when the amplitude of the signal (12) being transmitted by the line driver (20) requires it as determined by a comparator (18). Advantageously, this reduces the power dissipation in the line driver (10) by operating the line amplifier (20) the majority of the time from the lower supply voltage. A delay circuit (14) delays the signal to be amplified sufficient to allow the transitioning of the power supply voltages provided to the amplifier hysteresis of this power supply voltage switching may also be used to further reduce power dissipation.

Abstract: An upstream programmable gain amplifier (PGA) (114, 214) for a cable modem (100) having a programmable bias current. PGA (114, 214) includes a bias current-setting circuit (140, 240) coupled to a power amplifier stage (136, 236), the bias current-setting circuit (140, 240) adapted to program the bias current Ibias of the power amplifier stage (136, 236). The bias current-setting circuit (140) includes a bandgap generator (130, 230) having an external bias resistor R1 at the input. The bias current-setting circuit (140) may include a variable gain amplifier (VGA) (134), a digital-to-analog converter (DAC) (132), and a bias code generator (138). The bias current-setting circuit (240) may alternatively include a plurality of programmable resistors R1a, R1b . . . R1x coupled to a bias code generator (238).

Abstract: The present invention provides technical advantages as a class AB output driver (400) with minimal cross-over distortion. If the differential input to the driver is I+&dgr;I/2 and I−&dgr;I/2, then the current gain is the average of &bgr;n and &bgr;p, more specifically, (&bgr;n−&bgr;p)*I+((&bgr;n+&bgr;p)/2)* &dgr;I. The offset current (&bgr;n−&bgr;p)*I is taken out with a feedback loop.

Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Abstract: A programmable gain amplifier (10) has a differential input (12-13), a differential output (16-17), and a plurality of enable inputs (21, 31-34). The amplifier includes a plurality of transconductor sections (26-29), which each have input nodes coupled to the differential input, output nodes coupled to the differential output, and an enable node coupled to a respective enable signal. The transconductor sections have different gains, which are respective powers of two. Each transconductor section includes a transconductor circuit (51, 56) which is coupled in series with at least one current mirror circuit (52-53, 57-58). Each transconductor circuit has a transistor (121) with a class A quiescent current that is proportional to the corresponding gain, the transistor being sized to achieve an optimum current density for its quiescent current.

Abstract: A class ‘AB’ amplifier output stage has an active current bias source that provides base drive current to the output transistors that is proportional to the signal input voltage level. The output transistor currents are modulated with the input signal such that the quiescent supply current is reduced to a very small level.

Abstract: A method for adjusting the output response of a complementary bipolar operational amplifier includes: providing a first bipolar transistor 14; providing a second bipolar transistor 16 coupled to the first bipolar transistor 14; providing a first current source 26 coupled to a base of the first bipolar transistor 14; providing a second current source 28 coupled to a base of the second bipolar transistor 16; providing a third bipolar transistor 10 coupled to the base of the first bipolar transistor 14; providing a fourth bipolar transistor 12 coupled to the base of the second bipolar transistor 16; providing a first resistor 20 coupled between a base of the third transistor 10 and a common node; providing a second resistor 18 coupled between a base of the fourth transistor 12 and the common node; providing a capacitor 30 coupled to the common node; providing a first input stage current source 24 coupled to the first resistor 20; providing a second input stage current source 22 coupled to the fourth resistor 18;

Abstract: A low EMI bias current generator for cable modem applications has a distributed output stage with a steering input that controls the amount of bias current flowing through each transistor of a differential pair. A pair of resistors acts as a potentiometer controlling the amount of voltage seen across the input of the differential pair. The resistor pair controls the speed of transfer of bias current from one transistor to another such that the current transfer will take the form of a hyperbolic tangent that will allow a very gentle start-up.

Abstract: A current-to-current impedance converter re-circulates the driver transistor collector current back into the output current path to generate an error current that has two portions including a DC offset portion and a second order in 1/&bgr; portion. Since the error current has no first order in 1/&bgr; portion, the current-to-current ronverter exhbits very low distortion.

Abstract: An output stage (10) is provided having transistors of the same polarity type, which function to amplify the input signal at a wide range of frequencies, with low power consumption and low crossover distortion. By biasing the output transistors to remain on during both the positive and negative voltage swing of the input signal, low power consumption as well as low output crossover distortion is achieved. A high efficiency, low crossover distortion, current amplifier circuit for amplifying an input signal (VIN) in accordance with this present invention includes an output driver (12), a current source (IS1) and a translinear loop circuit (14). The output driver (12) includes a sourcing circuit (Q6). The current source (IS1), connected to the output driver (12), provides bias current to the sourcing circuit. The translinear loop circuit (14), connected to the output driver (12), receives the input signal (VIN).

Abstract: An output stage of a complementary bipolar operational amplifier includes: a first bipolar transistor 14; a second bipolar transistor 16 coupled to the first bipolar transistor 14; a third bipolar transistor 10; a fourth bipolar transistor 12; a first resistor 42 coupled between a base of the first bipolar transistor 14 and the third bipolar transistor 10; a second resistor 43 coupled between a base of the second bipolar transistor 16 and the fourth bipolar transistor 12; a first current source 26; a second current source 28; a third resistor 40 coupled between the first current source 26 and the third transistor 10; a fourth resistor 41 coupled between the second current source 28 and the fourth transistor 12; a fifth resistor 19 coupled between a base of the third transistor 10 and a common node; a sixth resistor 18 coupled between a base of the fourth transistor 12 and the common node; a first input stage current source 24 coupled to the base of the third transistor 10; and a second input stage current sou

Abstract: A method for fabricating a BiCMOS integrated circuit. The method includes the steps of forming in a single implantation step a base region 211 of a bipolar transistor and a p-well 212 of an n-channel MOS transistor; and forming in a single implantation step a collector contact well 213 of a bipolar transistor and an n-well 208 of a p-channel MOS transistor.

Abstract: A programmable gain amplifier (10) has a differential input (12-13), a differential output (16-17), and a plurality of enable inputs (21, 31-34). The amplifier includes a plurality of transconductor sections (26-29), which each have input nodes coupled to the differential input, output nodes coupled to the differential output, and an enable node coupled to a respective enable signal. The transconductor sections have different gains, which are respective powers of two. Each transconductor section includes a transconductor circuit (51, 56) which is coupled in series with at least one current mirror circuit (52-53, 57-58). Each transconductor circuit has a transistor (121) with a class A quiescent current that is proportional to the corresponding gain, the transistor being sized to achieve an optimum current density for its quiescent current.

Abstract: An amplifier slew rate boosting scheme for use with an amplifier having a closed-loop gain equal to or very near unity has one plate of a compensation capacitor conventionally coupled to an internal high impedance gain node, but has the other plate of the compensation capacitor unconventionally driven with a buffered version of the input signal. The voltage appearing across the compensation capacitor in response to changes in the input signal is significantly less than that achieved using conventional compensation architectures where the other plate of the compensation capacitor is coupled to an AC ground. Since very little current is required to charge the compensation capacitor, the tail current generated by the input stage can be used instead to charge parasitic capacitances within the amplifier to increase the slew rate.

Abstract: Responsive to an external load, an output stage (201) of an amplifier (200) in accordance with the present invention provides a current boosting scheme capable of generating a large output current while maintaining a low quiescent current. The output stage (201) includes a sink control circuit (204) coupled to the input terminal (202) for receiving the output of the input amplifier stage. A translinear loop circuit (210) is coupled to the sink control circuit (204), for receiving the sink pass-through current and for producing a source pass-through current. A current mirror circuit (222) is coupled to the translinear loop circuit (210) for receiving the source pass-through and for producing a bias current output therefrom. An output driver (230) is coupled to the current mirror circuit (222) and the sink control circuit (204), wherein the output driver (230) receives the bias output current and the sink pass-though current to provide an output current.

Abstract: A single pair differential amplifier circuit (90) provides signal amplification across the full amplifier power-supply voltage range. The differential amplifier circuit (90) is coupled to the first rail (122) and the second rail (124) and has a differential input (114 and 116) for receiving a common-mode input voltage. A bias circuit (126) is coupled to the differential amplifier circuit (90) for applying a bias voltage to the differential pair of transistors (102 and 104) such that the bias circuit (126) controls the threshold voltage of the differential pair of transistors (102 and 104) in the response to the common-mode input voltage. The bias circuit (126) turns differential pair of transistors (102 and 104) on when the common-mode input voltage is in a range extending from the first supply voltage to the second supply voltage.

Abstract: A Class-D switching amplifier (30, 40) having a ternary mode of operation. Signal processing (21, 22) is provided to eliminate the potential of crosstalk within one channel by introducing a time delay into the system. A susceptible crosstalk point is moved away from a zero-crossing point to a higher power level, which is advantageous in low-end audio applications. A time delay is introduced to one ramp signal (RAMPB) in the first implementation (30), and an in-sync generator (42) is utilized in another implementation (40) using offset switching in the comparitors (40, 42) to create the time delay (&Dgr;t).

Abstract: A rail-to-rail input stage (20) for an operational amplifier having a constant transconductance (Gm) over a common mode range. The input stage has a cross-coupled quad circuit (Q9, Q10, Q15, Q16) having an essentially infinite transconductance, and pair of transistors (Q5, 6) running at the same current as input transistors (Q1, Q2) when active, whereby the pair of transistors (Q5, Q6) establish a constant transconductance of the input stage (20).

Abstract: A Class-D switching amplifier (20) having a terinary modulation scheme implemented in an H-bridge configuration. The present invention has four states of operation, and achieves increased efficiency and reduced cost by delivering current to the load only when needed, and once delivered, maintaining the current. The Class-D switching amplifier eliminates the need for post amplifier filters.

Abstract: A low drop-out (LDO) voltage regulator (10) and system (100) including the same are disclosed. An error amplifier (38) controls the gate voltage of a source follower transistor (24) in response to the difference between a feedback voltage (VFB) from the output (VOUT) and a reference voltage (VREF). The source of the source follower transistor (24) is connected to the gates of an output transistor (12), which drives the output (VOUT) from the input voltage (VIN) in response to the source follower transistor (24). A current mirror transistor (14) has its gate also connected to the gate of the output transistor (12), and mirrors the output current at a much reduced ratio. The mirror current is conducted through network of transistors (18, 22), and controls the conduction of a first feedback transistor (28) and a second feedback transistor (35) which are each connected to the source of the source follower transistor (24) and in parallel with a weak current source (34).