Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Abstract: This is a driver circuit 100 for use in an integrated circuit 10 for driving two complimentary signals on output terminals 104 and 106. A single device, such as a Schottky diode 170, prevents voltage breakdown resulting from an externally supplied voltage on either output terminal 104, 106. The single device, such as Schottky diode 170, provides voltage breakdown protection for an output transistor 150 and a complimentary output transistor 152.The single device can be made larger than if two devices were used so that a voltage drop across the device resulting from normal forward current conduction is minimized.

Abstract: A method for reducing the parasitic capacitance and capacitive coupling of nodes (106) in a dielectrically isolated integrated circuit (100) using layout changes. A separate area of floating silicon (110) is created adjacent two or more dielectrically isolated nodes (106). The two or more nodes (106) are chosen that "slew together" (i.e., nodes that are required to change by the same voltage at the same time). The area of floating silicon (110) is created by placing an additional trench (112) around both of the dielectrically isolated nodes (106).

Abstract: An output stage of an amplifier circuit includes a sinking bipolar circuit 22 for sinking current from an external load 12; a sourcing MOS transistor 14 for sourcing current to the external load 12, a source of the MOS transistor 14 coupled to the sinking bipolar circuit 22 to form a common output node 34; a mirroring MOS transistor 16 having a gate coupled to a gate of the sourcing MOS transistor 14 such that current in the sourcing transistor 14 approximately mirrors current in the mirroring transistor 16; and a current mirror circuit 39 responsive to the mirroring transistor 16 and coupled to control current flow through the sinking bipolar circuit 22.

Abstract: A controller for a power converter wherein there is provided a comparator having an output terminal and first and second input terminals. A switch-mode power train is coupled to the output terminal and operable to receive an unregulated input voltage and provide a regulated output voltage. A feedback network coupled to the switch-mode power train provides a voltage to the first input of the comparator. A ramp circuit includes a first capacitor divider having a first capacitor connected from a first input node to a first midpoint node and a second capacitor connected from the first midpoint node to a first reference voltage node and a second capacitor divider including a third capacitor connected from a second input node to a second midpoint node and a fourth capacitor connected from the second midpoint node to the first reference node. A first switch couples the first or second midpoint node to the second input of said comparator.

Abstract: A circuit (10) and method for limiting output currents in a circuit having at least two output drivers (12,14) with outputs (16,18) on which first and second out-of-phase output currents are produced includes a current source (34) and a first current mirror (28). The first current mirror (28) has a first side (30) connected to sense a current in the output drivers and has a second side (32) connected to the current source (34). A magnitude of the current in the output drivers (12,14) produces a proportional voltage at a connection (52) between the second side (32) and the current source (34). First and second control transistors (40,42) are each connected to provide a control current to control respective output currents of the drivers (12,14), the first and second control transistors (40,42) being connected to receive an input signal (46) to pass the control current.

Abstract: An output stage of an amplifier circuit includes: a sinking bipolar circuit 23 for sinking current from an external load; a sourcing transistor 14 for sourcing current to the external load, the sourcing transistor 14 coupled in series with the sinking bipolar circuit 23, a common output node 34 is formed between the sourcing transistor 14 and the sinking bipolar circuit 23; a mirroring transistor 16 coupled to the sourcing transistor 14 such that current in the sourcing transistor 14 approximately mirrors current in the mirroring transistor 16; a current mirror circuit 39 responsive to the mirroring transistor 16 and coupled to control current flow through the sinking bipolar circuit 23; and a translinear bias circuit 48 coupled to the sinking bipolar circuit 23 for maintaining a minimum current in the bipolar circuit 23.

Abstract: A driver amplifier for a bus feeds single polarity signals of controlled slew rate to the bus. The slew rate control is effected by a feedback capacitor connected from the output to the input of the amplifier. A clamp is provided for selectively connecting the input of the amplifier through a low impedance path to a point of reference voltage so that when the amplifier is quiescent signals on the bus cannot be fed through the capacitor to turn on the amplifier. A current source and a switchable current sink are connected to the input of the amplifier to change the capacitor to produce the slew rate controlled transitions. Another driver amplifier of the same design but using components of the opposite conductivity type can be used to apply signals of the opposite polarity to the same bus.

Abstract: A bipolar operational amplifier circuit includes: a differential pair having a first transistor Q.sub.1 and a second transistor Q.sub.2 ; a third transistor Q.sub.6 having a first node coupled to a first node of the first transistor Q.sub.1 ; a fourth transistor Q.sub.9 having a first node coupled to a first node of the second transistor Q.sub.2 ; a fifth transistor Q.sub.8 having a first node coupled to the first transistor Q.sub.1 ; a sixth transistor Q.sub.11 having a first node coupled to the second transistor Q.sub.2 ; a current mirror 20 having a first branch coupled to a second node of the fifth transistor Q.sub.8 and a second branch coupled to a second node of the sixth transistor Q.sub.11 ; a seventh transistor Q.sub.27 having a base coupled to the first branch of the current mirror 20; an eighth transistor Q.sub.28 having a base coupled to the third transistor Q.sub.6 ; a ninth transistor Q.sub.20 having a first node coupled to a first node of the seventh transistor Q.sub.

Abstract: Low-side driver circuit (200) for data transmission applications includes external connection (202) for connecting and providing drive current to an external physical interface circuit. Sink transistor (210) forms an isolation from the physical interface circuit, and channels low-side drive current to external connection (202). Sink transistor (210) includes base (216), collector (208), and emitter (224). Emitter follower transistor (228) associates with sink transistor (210), and in conjunction with "A" input to the gate of transistor (228), sink transistor (210) controls the state of emitter follower transistor (228). Blocking transistor (206) associates with base (216) of sink transistor (210) to block the base of sink transistor (210) in the off state of sink transistor (210). Pull-down diodes (218) and (220) associate with base (216) of sink transistor (210) to pull down the voltage of the base when sink transistor (210) is in an off state.

Abstract: A boost mode controller with start up circuit includes: an inductor 12; a transistor 10 coupled to a first end of the inductor 12; a diode 16 having an anode coupled to the first end of the inductor 12; a capacitor 14 coupled to a cathode of the diode 16; a logic circuit 22 having an output coupled to a control node of the transistor 10; a comparator 28 having an output coupled to a first input of the logic circuit 22, a first input of the comparator 28 coupled to the capacitor 14, and a second input of the comparator 28 coupled to a reference node; and a counter 20 having an active low reset coupled to the output of the comparator 28 and an output coupled to a second input of the logic circuit 22.

Abstract: High-side physical interface driver circuit (10), for use in a variety of data transmission applications, includes an external connection (18) for connecting and providing drive current to an external physical interface. Output transistor (16) for channeling high-side drive current to external connection (18). Output transistor (16) includes base (18), collector (14), and emitter (24). Control transistor (28) controls the on state of output transistor (16) to supply high-side drive current to external connection (18). At least one shorting transistor (30) shorts base (19) of output transistor (16) to emitter (24), when high-side voltage reaches a predetermined minimum voltage level.

Abstract: Slew-rate limited differential drivers are useful for reliable data transmission on longer un-terminated cables with longer stub lengths. Slew-rate limit can be achieved by the ratio of a constant current to a capacitor means. In order to have equal rise and fall times, an equal amount of current is steered into the capacitor means in opposite directions. This architecture has unequal propagation delays on the transition edges. This mismatch is directly attributable to the signal transfer in current steering means. The slew-rate limited differential driver corrects this problem by delaying the rising edge by the required amount using a second capacitor means and a diode means. And hence, the preferred embodiment has a better skew on the output.

Abstract: A voltage regulator circuit includes: a first MOS transistor 12 coupled between a voltage supply line and an output node 44, the first MOS transistor 12 providing a stable voltage on the output node 44; a source follower 24 coupled to a gate of the first MOS transistor 12; an amplifier 38 coupled to a gate of the source follower 24 for controlling the response of the first MOS transistor 12; negative feedback circuitry coupled between the output node 44 and the amplifier 38, the feedback circuitry providing feedback to the amplifier 38; a current conveyer 46 coupled to the first MOS transistor 12; and positive feedback circuitry 26 coupled between the current conveyer 46 and the source follower 24.

Abstract: A voltage regulator circuit (10) is provided. Regulator circuit (10) includes an amplifier (18) with an emitter follower output stage (26). Emitter follower stage (26) is coupled to a gate of a PMOS transistor (28). The source of transistor (28) is coupled to an input voltage at a power supply rail (12). Regulator (10) provides an output at node (14) at a drain of transistor (28). The output at node (14) is divided by resistors (30 and 34) and provided in a negative feedback loop to an input of amplifier (18). A reference voltage (22) is also provided to a second input of amplifier (18) such that the output at node (14) is a regulated voltage.

Abstract: A semiconductor transistor device includes a first doped region 34 of a first conductivity type; a second doped region 30 of the first conductivity type formed at the surface of the first doped region 34, the second doped region 30 has a higher doping concentration than the first doped region 34; a source region 24 of a second conductivity type formed at the surface of the second doped region 30; a lightly doped drain region 28 of the second conductivity type surrounding the first doped region 34, the lightly doped drain region 28 has a lower doping concentration than the source region 24, the lightly doped drain region 28 is spaced apart from the second doped region 30; a buried layer 40 of the second conductivity type below the first doped region 34 and coupled to the lightly doped drain region 28; and a gate 32 overlying and spaced apart from the first doped region 34 and the second doped region 30.

Abstract: A method of fabricating a semiconductor device containing a HVDMOS transistor and a LVDMOS transistor and the device which includes providing a region of semiconductor material of a first conductivity type and forming a high voltage DMOS transistor disposed in the region. A relatively low voltage DMOS transistor is also disposed in that region and electrically isolated from the high voltage DMOS transistor. The low voltage DMOS transistor has spaced apart source and drain regions disposed in the region of semiconductor material and a back gate region of the first conductivity type disposed in the region of semiconductor material between the source and drain regions. The back gate region is electrically coupled to the region of semiconductor material. The region of semiconductor material includes a surface, the source, drain and back gate regions extending to that surface.

Abstract: A therapeutical method for treating chronic arteriosclerosis obliterans in particularly selected patients with severely disabling intermittent claudication is disclosed, which comprises administering propionyl L-carnitine or a pharmacologically acceptable salts thereof.

Abstract: This invention relates to differential bus drivers for use in, for example, communication systems. The driver achieves highly symmetrical wave forms at the output stage for both high and low side drivers. In addition, the layout of components of the high and low side drivers is substantially identical which allows production of the driver as an integrated circuit with a simple layout.

Abstract: In a summing comparator (10) in which one differential input voltage received by one differential pair (18) is dependent on temperature variations, such as across a resistor (12) with a large temperature coefficient, the dependence on temperature is offset by introducing cancelling temperature dependence in the other differential pairs (14, 16).