Abstract: An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage.

Abstract: A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output impedance. Included with the switched current source is an error correction transistor and a resistor that cooperate to feed a current back through a bias transistor to correct an error that generally results from the current gains or ?'s of transistors within the switched current source. To accomplish this, however, the resistor is selected to have a value that is sufficiently large such that current from the error correction transistor flows back through the bias transistor.

Abstract: A track-and-hold circuit capable of tracking an analog input signal and holding a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. A first capacitor is provided, having a first terminal connected to a power supply terminal. Tracking circuitry operates when in an on state to apply through a resistor a tracking voltage to a second terminal of the first capacitor that corresponds to the voltage of the analog input signal, by applying the tracking voltage to a first terminal of the resistor, the second terminal of the resistor being connected to the second terminal of the first capacitor. A switch, responsive to the track signal and the hold signal, operates to switch the tracking circuitry to an on state in response to the track signal and to an off state in response to the hold signal, the time of change from the track signal to the hold signal comprising the sampling instant.

Abstract: The use of 7-ter-butoxyiminomethylcamptothecin is described in the preparation of a medicament useful for the treatment of uterine neoplasms, particularly cancer of the endometrium and of the neck of the womb.

Abstract: A digital data interface system comprises a data transmitter configured to transmit a data word across a plurality of data lines. The data word can comprise a plurality of digital data bits having a bit number order from a lowest bit number to a highest bit number with the lowest ordered bit numbers having higher noise content and the highest ordered bit numbers having higher harmonic content. The system also comprises an encoder configured to arrange the plurality of digital data bits as serialized data sets to be transmitted over each of the plurality of data lines by the data transmitter with consecutive data bits of at least one serialized data set being matched such that bits with the higher harmonic content are matched with bits of the higher noise content to substantially mitigate of at least one of the noise content and the harmonic content of the data word.

Abstract: A track-and-hold or sample-and-hold (S/H) circuit for an analog-to-digital converter (ADC) is provided. A difference between the disclosed S/H circuit and conventional S/H circuits is the use of a peaking circuit. This peaking circuit generally provides increased current to switching transistor when transitioning between track and hold which can increase the Spurious-Free Dynamic Range (SFDR) as low frequencies, by as much as 15 dB.

Abstract: A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit.

Abstract: Various systems and methods for signal amplification are disclosed. For example, some embodiments of the present invention provide differential amplifiers that include dual transconductance characteristics. Such amplifiers include two dual input operational amplifiers that each include two input sets. A first of the input sets exhibits a first transconductance and a second of the input sets exhibits a second transconductance. The two dual input operational amplifiers are configured such that to a common mode signal, the amplifier exhibits an overall transconductance that is the difference between the first transconductance and the second transconductance. In contrast, to a differential signal, the overall transconductance is the sum of the first transconductance and the second transconductance.

Abstract: One embodiment of the present invention includes a pipelined analog-to-digital converter (ADC) comprising a plurality of pipeline stages. At least one of the plurality of pipeline stages comprises a feedback transistor-follower combination interconnected between a positive source voltage and a summation node and configured to set a voltage of the summation node approximately equal to a sample-and-hold voltage associated with a preceding one of the plurality of pipeline stages. The at least one of the plurality of pipeline stages also comprises a current mirror coupled to the feedback transistor-follower combination configured to provide a first current that is approximately equal to a second current that is associated with the feedback transistor-follower combination. The at least one of the plurality of pipeline stages further comprises an output resistor configured to set an output voltage of the respective at least one of the plurality of pipeline stages based on the first current.

Abstract: One embodiment of the present invention includes a pipelined analog-to-digital converter (ADC) comprising a plurality of pipeline stages. At least one of the plurality of pipeline stages comprises a feedback transistor-follower combination interconnected between a positive source voltage and a summation node and configured to set a voltage of the summation node approximately equal to a sample-and-hold voltage associated with a preceding one of the plurality of pipeline stages. The at least one of the plurality of pipeline stages also comprises a current mirror coupled to the feedback transistor-follower combination configured to provide a first current that is approximately equal to a second current that is associated with the feedback transistor-follower combination. The at least one of the plurality of pipeline stages further comprises an output resistor configured to set an output voltage of the respective at least one of the plurality of pipeline stages based on the first current.

Abstract: A track-and-hold circuit capable of tracking an analog input signal and holding a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. A first capacitor is provided, having a first terminal connected to a power supply terminal. Tracking circuitry operates when in an on state to apply through a resistor a tracking voltage to a second terminal of the first capacitor that corresponds to the voltage of the analog input signal, by applying the tracking voltage to a first terminal of the resistor, the second terminal of the resistor being connected to the second terminal of the first capacitor. A switch, responsive to the track signal and the hold signal, operates to switch the tracking circuitry to an on state in response to the track signal and to an off state in response to the hold signal, the time of change from the track signal to the hold signal comprising the sampling instant.

Abstract: An improved latched comparator, including a track mode circuit, a latch and a latch and track select circuit. The track mode circuit includes two transistors having their sources connected together, and their respective gates receiving a respective first and second input, and their drains connected to the power supply by respective resistors. The latch includes a further two transistors having their sources connected together, a gate of each connected to a drain of the other, and their drains connected to a respective one of the common connection node of the first transistor and the first resistor, and the second transistor and the second resistor.

Abstract: Is described the use of propionyl L-carnitine, or a pharmaceutical salt thereof, for preparing a medicament for the prevention and/or treatment of left ventricular hypertrophy in ESRD or dialysed patients.

Abstract: A digital data interface system comprises a data transmitter configured to transmit a data word across a plurality of data lines. The data word can comprise a plurality of digital data bits having a bit number order from a lowest bit number to a highest bit number with the lowest ordered bit numbers having higher noise content and the highest ordered bit numbers having higher harmonic content. The system also comprises an encoder configured to arrange the plurality of digital data bits as serialized data sets to be transmitted over each of the plurality of data lines by the data transmitter with consecutive data bits of at least one serialized data set being matched such that bits with the higher harmonic content are matched with bits of the higher noise content to substantially mitigate of at least one of the noise content and the harmonic content of the data word.

Abstract: Various systems and methods for signal amplification are disclosed. For example, some embodiments of the present invention provide differential amplifiers that include dual transconductance characteristics. Such amplifiers include two dual input operational amplifiers that each include two input sets. A first of the input sets exhibits a first transconductance and a second of the input sets exhibits a second transconductance. The two dual input operational amplifiers are configured such that to a common mode signal, the amplifier exhibits an overall transconductance that is the difference between the first transconductance and the second transconductance. In contrast, to a differential signal, the overall transconductance is the sum of the first transconductance and the second transconductance.

Abstract: A clock signal preamplifier comprises complementary pairs of differentially coupled transistors, with an output signal coupled to an inverter further comprising a totem-pole arrangement of complementary MOSFET transistors. The input signal to the preamplifier is typically sinusoidal, and the output signal is rectangular. Preferably, the differentially coupled transistors are bipolar, and a pair of diode clamper circuits with bipolar transistors is preferably coupled to the complementary pairs of differentially coupled transistors. A reference voltage source is coupled to the control terminals of the clamper transistors. A reference voltage source, which preferably comprises a totem-pole arrangement of complementary MOSFET transistors with its output node is coupled to its input node, provides a reference voltage for the diode clamper circuits.

Abstract: A reference voltage circuit having an open-loop buffer driven by a matching buffer included within a closed-loop, generates a stable differential or single-ended voltage while minimizing signal-dependent short-term and long-term drift. The open-loop buffer may be a replica of the closed-loop buffer, reducing the effect of a signal coupled on the voltage reference lines. The reference voltage circuit may be adapted for a switched capacitor ADC.

Abstract: The use of 7-ter-butoxyiminomethylcamptothecin is described in the preparation of a medicament useful for the treatment of uterine neoplasms, particularly cancer of the endometrium and of the neck of the womb.

Abstract: A dual output buck-boost power converter operates with a single inductor to achieve high efficiency with automatic or inherent load balancing. Switches associated with the opposite polarity outputs are driven based on feedback signals, with one feedback signal being a reference voltage and another feedback signal being related to an opposite polarity output. The opposite polarity feedback signal is provided to a comparator with a reversed polarity to achieve a simple balanced control that maintains polarity outputs. The power converter delivers power to each output with each switching cycle and uses a single inductor to achieve high efficiency performance.

Abstract: Is described a method of treating left ventricular hypertrophy comprising administering an effective amount of propionyl L-carnitine, or a pharmaceutical salt thereof, to ESRD or dialysed patients in need of such treatment.