Abstract: A high operating voltage bipolar transistor (42) includes a base including a first region (52) of a lightly doped layer (44) of semiconductor material of a first conductivity type. The transistor (42) also includes a collector including a buried layer (50) and a collector region (48). The lightly doped layer (44) is formed over the buried layer (50) and the collector region (48) extends through the lightly doped layer (44) and contacts the buried layer (50). The transistor (42) also includes an emitter formed in the base. The transistor (42) provides a high operating voltage without requiring an increased thickness epitaxial layer or additional processing steps. A high Hfe transistor and high voltage Schottky diode are also described.

Abstract: A circuit and method for sensing and limiting current. An output driving transistor (M1) is coupled between a circuit output terminal and a power supply terminal. A replicator circuit is formed in a cross-coupled quad configuration from bipolar transistors (Q11, Q12, Q13 and Q14) and is coupled to a second transistor (M2) which generals a voltage proportional to the current flowing in the output driving transistor (M1). The current sensing circuit generates an output current which is proportional to the current flowing in the output driving transistor multiplied by a ratio of the sizes of the second transistor and the output driving transistor. In a current limiting configuration, the output of the cross-coupled quad is used to reset a flip-flop (FF1) that drives the gate terminal of the output transistor (M1), thus shutting down the output transistor before it is damaged due to excess current. The circuitry of the invention may be applied to a high side driver or a low side driver output circuit.

Abstract: A switch mode power converter (10) is provided. Converter (10) includes a switching cell (12) that transforms an input voltage at input port (22) to an output voltage at output port (24). Switching cell (12) is controlled by a fixed-period, variable on-time control signal from summing comparator (14). The period of the control signal is set by a driving circuit (20). The on time is set by first and second feedback circuits (16) and (18). First feedback circuit (16) provides a fast transient response. Second feedback circuit (18) provides an stable dc steady-state operating point.

Abstract: A low leakage ESD network (24) is provided for protecting a semiconductor device (22). The ESD network (24) comprises an ESD circuit (28) and a bias circuit (30). The ESD circuit (28) is connected to an input of the semiconductor device (22). The ESD circuit (28) is operable to protect the input of the semiconductor device (22) against electro-static discharge. The bias circuit (30) is connected to the input of the semiconductor device (22) and to the ESD circuit (28). The bias circuit (30) is operable to actively bias the ESD circuit (28) such that a voltage difference across each current leakage path in the ESD circuit (28) is held substantially equal to zero volts during normal operation of the semiconductor device (22).

Abstract: A circuit and method for sensing and limiting current. A resistor (R1) is used to generate a voltage (V1) proportional to the current flowing in an output transistor (M1). A comparator is formed in a cross coupled quad configuration from bipolar transistors (Q11, Q12, Q13 and Q14) and is coupled to the resistor (R1). When the current in the resistor (R1) generates a voltage in excess of a threshold voltage for the cross coupled quad circuit, the cross coupled quad generates an output indicating the threshold has been reached. In a current limiting configuration, the output of the cross coupled quad is used to reset a flip-flop (FF1) that drives the gate terminal of the output transistor (M1), thus shutting down the output transistor before it is damaged due to excess current. The threshold voltage that triggers the cross coupled quad is proportional-to-absolute-temperature.

Abstract: An amplifier circuit (10) is provided. The amplifier (10) includes an amplifier stage (14) coupled to an output stage (18). Output stage (18) comprises a sourcing circuit (20) and a sinking circuit (22). The current in sinking circuit (22) is approximately mirrored at low current in mirror circuit (34). At higher currents, resistor (36) maintains the current in mirror circuit (34) below the current in sinking circuit (22). A diode (38) diverts current to mirror circuit (34) to aid sinking circuit (22) in sinking current from a load (12). A current source (29) supplies current to sourcing circuit (20) and mirror circuit (34). A control signal output by amplifier stage (14) causes mirror circuit (34) to draw or not draw current from current source (29). If mirror circuit (34) draws current from current source (29), output stage (18) sinks current in sinking circuit (22). If mirror circuit (34) does not draw current from current source (29), output stage (18) sources current through sourcing circuit (20).

Abstract: An amplifier circuit (10) is provided. Amplifier (10) has an amplifier stage (14) that is coupled to control an output stage (18). Output stage (18) includes a sourcing circuit (20) and a sinking circuit (22). Output stage (18) also includes a mirror circuit (42) that is coupled to an output of amplifier stage (14). Output stage (18) also includes a current balancing circuit (30) coupled to mirroring circuit (42) and sourcing circuit (20). Mirroring circuit (42) draws current from balancing circuit (30) in response to a first predetermined output from amplifier stage (14) such that balancing circuit (30) causes an insignificant current to flow in sourcing circuit (20). Thus amplifier (10) operates to sink current from an external load (12). Alternatively, mirroring circuit (42) may draw an insignificant current from balancing circuit (30) in response to a second predetermined output of the amplifier stage (14). This causes a significant current flow in sourcing circuit (20).