Abstract: Methods and systems for declarative animation timelines are disclosed. In some embodiments, a method includes generating a declarative timeline data structure, creating an animation of an image along the timeline, and adding a declarative command corresponding to the animation into the declarative data structure. The method also includes, in response to a request to render the animation, generating a run-time command corresponding to the declarative command and executing the run-time command. In other embodiments, a method includes receiving a request to render an animation, wherein the animation includes a declarative timeline data structure having a plurality of commands, parsing the plurality of commands, passing each of the parsed plurality of commands to an animation function, receiving a plurality of run-time commands in response to said passing, and causing a rendering the animation by causing an execution of the plurality of run-time commands.

Abstract: Methods and systems for parameterizing animation timelines are disclosed. In some embodiments, a method includes displaying a representation of a timeline configured to animate a first image in a graphical user interface, where the timeline includes a data structure having one or more commands configured to operate upon a first property of the first image. The method also includes creating a parameterized timeline by replacing a reference to the first image within the timeline with a placeholder. The method includes, in response to a request to animate a second image, storing an entry in a dictionary of key and value pairs. The method further includes animating the second image by replacing the placeholder in the parameterized timeline with the reference to the second image during execution of the parameterized timeline.

Abstract: Methods and systems for using artwork to develop computer applications in ways that preserve the artwork's appearance and layout, including by importing the artwork and selectively replacing potions with functional components. One embodiment comprises a method for developing an application that involves displaying artwork in a design view area. The method may involve displaying artwork comprising a list representation comprising a plurality of list item representations and identifying each list item representation as a group of one or more subitem representations. The method may further comprise determining a list layout for list items using the list item representations of the artwork and inserting a list as a component in the design view area. This list may determine or otherwise be used to determine the positions of either the list item representations or list items replacing the list item representations. These positions may be determined based on the list layout that was determined.

Abstract: A multi-core die is provided that allows packets to be communicated across the die using resources of a packet switched network and a circuit switched network.

Abstract: Systems and methods which implement declarative language for specifying states within imperative code are shown. According to embodiments an application program developer declaratively identifies one or more states within the imperative code of the application program. Declarative language identifying a particular state of an application program may both operate to identify the state and to describe the state so that the state may be selected or “jumped to” without a user having to navigate the application program flow to arrive at the state. Particular states may be described using a difference or “delta” between the particular state and another state, such as a base state. Transitions may be implemented between states, such as to provide animation, fading, color change, et cetera.

Abstract: Systems and methods which facilitate search engine discovery of and/or access to application program content are shown. Declarative code may be provided within the procedural code of a rich Internet application in order to identify various states, and their associated content, of the rich Internet application. A Web crawler may identify content associated with a rich Internet application using the foregoing information. Likewise, direct access to rich Internet application states associated with the identified content may be provided using the foregoing information. A translation module may be provided for interfacing between a Web crawler and a rich Internet application.

Abstract: In one embodiment, the invention includes a method for compressing video data using redundant binary mathematics. Other embodiments are described and claimed.

Abstract: Systems and methods which implement declarative language for specifying states within imperative code are shown. According to embodiments an application program developer declaratively identifies one or more states within the imperative code of the application program. Declarative language identifying a particular state of an application program may both operate to identify the state and to describe the state so that the state may be selected or “jumped to” without a user having to navigate the application program flow to arrive at the state. Particular states may be described using a difference or “delta” between the particular state and another state, such as a base state. Transitions may be implemented between states, such as to provide animation, fading, color change, et cetera.

Abstract: A method for providing an Integrated Development Environment comprises receiving input from a user identifying an area containing an edge shared by two or more objects, wherein the shared edge includes two or more individual edges corresponding to the objects, and visibly separating the two or more individual edges in a localized exploded view responsive to the receiving.

Abstract: Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.

Abstract: Systems and methods which facilitate search engine discovery of and/or access to application program content are shown. Declarative code may be provided within the procedural code of a rich Internet application in order to identify various states, and their associated content, of the rich Internet application. A Web crawler may identify content associated with a rich Internet application using the foregoing information. Likewise, direct access to rich Internet application states associated with the identified content may be provided using the foregoing information. A translation module may be provided for interfacing between a Web crawler and a rich Internet application.

Abstract: Systems and methods which facilitate search engine discovery of and/or access to application program content are shown. Declarative code may be provided within the procedural code of a rich Internet application in order to identify various states, and their associated content, of the rich Internet application. A Web crawler may identify content associated with a rich Internet application using the foregoing information. Likewise, direct access to rich Internet application states associated with the identified content may be provided using the foregoing information. A translation module may be provided for interfacing between a Web crawler and a rich Internet application.

Abstract: For one disclosed embodiment, a converter converts 2N-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value. The converter includes N comparators, each determining whether the number of bits in the data having the predetermined logical value exceeds a respective one of a plurality of reference values. The N-bit value is generated based on the outputs of the comparators. For another disclosed embodiment, a first delay element delays a signal based on a number of bits in a data value having a predetermined logical value, and a second delay element delays the signal based on a number of bits in a reference value having the predetermined logical value. A comparator then generates a bit value based on the delayed signals.

Abstract: A multi-core die is provided that allows packets to be communicated across the die using resources of a packet switched network and a circuit switched network.

Abstract: A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.

Abstract: An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.

Abstract: In one embodiment, the invention includes a method for compressing video data using redundant binary mathematics. Other embodiments are described and claimed.

Abstract: A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic 0 carry-in and a logic 1 carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.

Abstract: A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.