Abstract: A server-side control object processes and generates a client-side user interface element for display on a web page. Multiple server-side control objects may be combined into a hierarchy of server-side control objects that cooperate to generate the resulting authoring language code, such as HTML, for display of a web page on a client. The operation of processing the client-side user interface element may include at least one of an event handling operation, a postback data handling operation, a data binding operation, and a state management operation. The state management operation relates to the state of a server-side control object.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Abstract: Embodiments of the present invention generally relate to an adder. In embodiments, the adder may include two adder circuits which each process a segment of a first number and a second number. The second adder, for processing the higher order digits, may be operated at a lower voltage supply level than the first adder for processing lower order digits. Accordingly, power savings may be accomplished with a nominal time delay penalty.

Abstract: Embodiments of the present invention generally relate to logic circuitry that implements both static logic and dynamic logic. In embodiments, static logic is implemented for functions which are non-performance critical and dynamic logic is implemented for functions that are performance critical. Accordingly, power savings can be realized.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Abstract: An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Abstract: In a computer environment, a new storage and delivery data format for multimedia object sets increases performance and improves the user experience by reducing the transactions needed to retrieve a set of n objects from n to 1. The object data is interleaved with data definition entries identifying respective object data into a data format comprising a single stream for storage and/or delivery. The data format eliminates the need for multiple, asynchronous transactions thus reducing latency in the data transfer process. Moreover, the data format allows for optimization of how the object data is prioritized and interleaved to achieve desired performance objectives upon delivery of the multimedia objects.

Abstract: A noise canceling circuit is provided in a dynamic circuit that includes a high fan-in domino gate. The noise canceling circuit decouples noise from neighboring wires in the dynamic circuit that is injected into a wire that controls the domino gate.

Abstract: A transition encoded dynamic bus includes an encoder circuit at the input to the bus and a decoder circuit at the output to the bus. The encoder circuit generates a signal indicative of a transition at the input to the bus rather than the actual value at the input. The decoder circuit decodes the transition encoded information to track the appropriate value to be output from the bus.

Abstract: An adjustable locking strap apparatus for locking an elongate object includes a first loop, a second loop, and an adjustable strap extending therebetween. The loops can be fit about ends of the elongate object. One loop could be adjusted adjusted for proper size. The strap extending between the loops can be adjusted between the loops so that when the first and second loops are positioned about the elongate object, the strap is sized to prevent either loop from being removed from the object. A lock is interconnected with the adjustable loop and strap for securing the size of the adjustable loop and strap. A tether portion can secure the locking strap to a fixed object. A stopper on the tether can be positioned within a car, and the window rolled up to retain the locking strap within a car. In other embodiments, two straps with loops at one end and stoppers at the other end can used. One loop is positioned about an end of the elongate object and the strap is retained in a housing.

Abstract: An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Abstract: A hierarchical clock distribution system includes a global clock grid that distributes a clock signal to a plurality of regional clock grids. Each of the regional clock grids then distributes the signal to a plurality of corresponding loads. The regional clock grids utilize salphasic clocking techniques to distribute the clock signal to the corresponding loads. The global grid achieves low skew based on the periodicity of the clock signal, rather than the dominance of a standing wave. The electrical distance to termination within the regional clock grids is preferably kept low to avoid the occurrence of phase change regions on the regional grids. In one approach, the regional grids are each driven at multiple points in a symmetrical fashion to reduce the electrical distance to termination.

Abstract: A noise canceling circuit is provided in a dynamic circuit that includes a high fan-in domino gate. The noise canceling circuit decouples noise from neighboring wires in the dynamic circuit that is injected into a wire that controls the domino gate.

Abstract: A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.

Abstract: A hierarchical clock distribution system includes a global clock grid that distributes a clock signal to a plurality of regional clock grids. Each of the regional clock grids then distributes the signal to a plurality of corresponding loads. The regional clock grids utilize salphasic clocking techniques to distribute the clock signal to the corresponding loads. The global grid achieves low skew based on the periodicity of the clock signal, rather than the dominance of a standing wave. The electrical distance to termination within the regional clock grids is preferably kept low to avoid the occurrence of phase change regions on the regional grids. In one approach, the regional grids are each driven at multiple points in a symmetrical fashion to reduce the electrical distance to termination.

Abstract: A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

Abstract: In an embodiment, a dynamic bus includes a dynamic bus repeater with a noise margin of about Vcc/2. The bus repeater splits the bus into front and rear segments. The front segment pre-charges while the rear segment evaluates, and vice versa. The dynamic bus repeater hides the pre-charge signal propagated from the front segment from the rear segment while the rear segment is evaluating.

Abstract: A high performance interconnect that utilizes dynamic driver technology is capable of reduced power operation during periods of low data switching activity. Circuitry is provided that limits the performance of an evaluation operation in the dynamic driver circuitry to clock cycles during which a present input bit of the interconnect differs from a previous input bit. Thus, the evaluation operation and subsequent precharge of the driver output is performed sparingly during periods of low data switching activity. An output circuit is also provided for decoding the data stream flowing through the interconnect at the receiver end thereof. Using the principles of the present invention, it is possible to achieve the performance advantages of dynamic drivers with the switching activity of interconnects that use static CMOS technology.