Abstract: A transition encoded dynamic bus includes an encoder circuit at the input to the bus and a decoder circuit at the output to the bus. The encoder circuit generates a signal indicative of a transition at the input to the bus rather than the actual value at the input. The decoder circuit decodes the transition encoded information to track the appropriate value to be output from the bus.

Abstract: A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.

Abstract: An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.

Abstract: A cutting system that includes a rotary blade cartridge that can be interchangeably used with a variety of cutting tools is disclosed. The cartridge houses a rotary blade assembly that is maintained in a secure and safe retracted state and that can be activated when the cartridge is inserted into a cutting tool. Activating a plunger of any of the cutting tools causes a piston of the rotary blade assembly to move the blade to an operative cutting position protruding from an aperture provided in the cartridge housing. Deactivating the plunger causes the blade to be return to its retracted and inoperative position within the housing. Cutting tools of the invention include rail cutters such as a primary workstation and a compact workstation, circle cutters, elliptical cutters, and freeform cutters. Each cutting tool is capable of receiving a rotary blade cartridge. Cartridges are freely interchangeable between the cutting tools.

Abstract: For one disclosed embodiment, a converter converts 2N-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value. The converter includes N comparators, each determining whether the number of bits in the data having the predetermined logical value exceeds a respective one of a plurality of reference values. The N-bit value is generated based on the outputs of the comparators. For another disclosed embodiment, a first delay element delays a signal based on a number of bits in a data value having a predetermined logical value, and a second delay element delays the signal based on a number of bits in a reference value having the predetermined logical value. A comparator then generates a bit value based on the delayed signals.

Abstract: A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.

Abstract: A sense amplifier includes a storage element and logic circuitry to transition encode an output signal.

Abstract: Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.

Abstract: Techniques for using gravity in applications such as drilling and logging. Techniques are present for (1) gravity well logging using gravity sensors arrays; (2) creating density pseudosections using gravity measurements; (3) performing Gravity Measurement While Drilling (GMWD) using single or multiple gravity sensors; and (4) geosteering using GMWD.

Abstract: A network-based distributed application system is provided in accordance with the present invention for enabling services to be established locally on a client system. The system may include an application and presentation logic, at least a portion of which is interchangeably processed by a server or a client without modification to the portion. The core functionality provided by the application may be preserved between the client and the server wherein improved network performance may provided along with improved offline service capabilities.

Abstract: A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic 0 carry-in and a logic 1 carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.

Abstract: A single ended current sensed bus with novel static power free receiver circuit is described herein. In one embodiment, a receiver circuit example includes a latch circuit to latch values for a first output and a second output during an evaluation phase in response to an input, a pre-charge circuit coupled to the latch circuit to pre-charge the latch circuit during a pre-charge phase, and a static power dissipation blocking (SPDB) circuit coupled to the pre-charge circuit and the latch circuit to substantially block static power from being dissipated during the pre-charge phase. Other methods and apparatuses are also described.

Abstract: An adjustable locking strap apparatus for locking an elongate object includes a first loop, a second loop, and an adjustable strap extending therebetween. The loops can be fit about ends of the elongate object. One loop could be adjusted adjusted for proper size. The strap extending between the loops can be adjusted between the loops so that when the first and second loops are positioned about the elongate object, the strap is sized to prevent either loop from being removed from the object. A lock is interconnected with the adjustable loop and strap for securing the size of the adjustable loop and strap. A tether portion can secure the locking strap to a fixed object. A stopper on the tether can be positioned within a car, and the window rolled up to retain the locking strap within a car. In other embodiments, two straps with loops at one end and stoppers at the other end can used. One loop is positioned about an end of the elongate object and the strap is retained in a housing.

Abstract: One or more server-side control objects provide server-side processing of postback input received from client-side user interface elements in a request from a client. Such input may include without limitation postback data and postback events generated from a web page on a client and received by a server in an HTTP request. A hierarchy of server-side control objects can cooperate to process the postback input and to generate the resulting authoring language code, such as HTML. Server-side events can also result from the server-side processing of postback input. In addition to processing postback input, server-side processing may include, without limitation, state management of server-side control objects and binding data to and from server-side database. After the processing and generating operations, the server-side control object hierarchy is terminated until a subsequent request is received from the client.

Abstract: A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

Abstract: In an embodiment, a dynamic bus includes a dynamic bus repeater with a noise margin of about Vcc/2. The bus repeater splits the bus into front and rear segments. The front segment pre-charges while the rear segment evaluates, and vice versa. The dynamic bus repeater hides the pre-charge signal propagated from the front segment from the rear segment while the rear segment is evaluating.

Abstract: A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.

Abstract: According to some embodiments, provided are a static low-swing driver circuit to receive a full-swing input signal, to convert the full-swing input signal to a low-swing signal, and to transmit the low-swing signal, and a dynamic receiver circuit to receive the low-swing signal and to convert the low-swing signal to a full-swing signal. Also provided may be an interconnect coupled to the driver circuit and to the receiver circuit, the interconnect not comprising a repeater and to receive the low-swing signal from the driver circuit and to transmit the low-swing signal to the receiver circuit.

Abstract: A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

Abstract: An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.