Abstract: A network-based distributed application system is provided in accordance with the present invention for enabling services to be established locally on a client system. The system may include an application and presentation logic, at least a portion of which is interchangeably processed by a server or a client without modification to the portion. The core functionality provided by the application may be preserved between the client and the server wherein improved network performance may provided along with improved offline service capabilities.

Abstract: A single ended current sensed bus with novel static power free receiver circuit is described herein. In one embodiment, a receiver circuit example includes a latch circuit to latch values for a first output and a second output during an evaluation phase in response to an input, a pre-charge circuit coupled to the latch circuit to pre-charge the latch circuit during a pre-charge phase, and a static power dissipation blocking (SPDB) circuit coupled to the pre-charge circuit and the latch circuit to substantially block static power from being dissipated during the pre-charge phase. Other methods and apparatuses are also described.

Abstract: An adjustable locking strap apparatus for locking an elongate object includes a first loop, a second loop, and an adjustable strap extending therebetween. The loops can be fit about ends of the elongate object. One loop could be adjusted adjusted for proper size. The strap extending between the loops can be adjusted between the loops so that when the first and second loops are positioned about the elongate object, the strap is sized to prevent either loop from being removed from the object. A lock is interconnected with the adjustable loop and strap for securing the size of the adjustable loop and strap. A tether portion can secure the locking strap to a fixed object. A stopper on the tether can be positioned within a car, and the window rolled up to retain the locking strap within a car. In other embodiments, two straps with loops at one end and stoppers at the other end can used. One loop is positioned about an end of the elongate object and the strap is retained in a housing.

Abstract: One or more server-side control objects provide server-side processing of postback input received from client-side user interface elements in a request from a client. Such input may include without limitation postback data and postback events generated from a web page on a client and received by a server in an HTTP request. A hierarchy of server-side control objects can cooperate to process the postback input and to generate the resulting authoring language code, such as HTML. Server-side events can also result from the server-side processing of postback input. In addition to processing postback input, server-side processing may include, without limitation, state management of server-side control objects and binding data to and from server-side database. After the processing and generating operations, the server-side control object hierarchy is terminated until a subsequent request is received from the client.

Abstract: A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

Abstract: In an embodiment, a dynamic bus includes a dynamic bus repeater with a noise margin of about Vcc/2. The bus repeater splits the bus into front and rear segments. The front segment pre-charges while the rear segment evaluates, and vice versa. The dynamic bus repeater hides the pre-charge signal propagated from the front segment from the rear segment while the rear segment is evaluating.

Abstract: A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.

Abstract: According to some embodiments, provided are a static low-swing driver circuit to receive a full-swing input signal, to convert the full-swing input signal to a low-swing signal, and to transmit the low-swing signal, and a dynamic receiver circuit to receive the low-swing signal and to convert the low-swing signal to a full-swing signal. Also provided may be an interconnect coupled to the driver circuit and to the receiver circuit, the interconnect not comprising a repeater and to receive the low-swing signal from the driver circuit and to transmit the low-swing signal to the receiver circuit.

Abstract: A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

Abstract: An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.

Abstract: A server-side control object processes and generates a client-side user interface element for display on a web page. Multiple server-side control objects may be combined into a hierarchy of server-side control objects that cooperate to generate the resulting authoring language code, such as HTML, for display of a web page on a client. The operation of processing the client-side user interface element may include at least one of an event handling operation, a postback data handling operation, a data binding operation, and a state management operation. The state management operation relates to the state of a server-side control object.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Abstract: Embodiments of the present invention generally relate to logic circuitry that implements both static logic and dynamic logic. In embodiments, static logic is implemented for functions which are non-performance critical and dynamic logic is implemented for functions that are performance critical. Accordingly, power savings can be realized.

Abstract: Embodiments of the present invention generally relate to an adder. In embodiments, the adder may include two adder circuits which each process a segment of a first number and a second number. The second adder, for processing the higher order digits, may be operated at a lower voltage supply level than the first adder for processing lower order digits. Accordingly, power savings may be accomplished with a nominal time delay penalty.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Abstract: An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Abstract: In a computer environment, a new storage and delivery data format for multimedia object sets increases performance and improves the user experience by reducing the transactions needed to retrieve a set of n objects from n to 1. The object data is interleaved with data definition entries identifying respective object data into a data format comprising a single stream for storage and/or delivery. The data format eliminates the need for multiple, asynchronous transactions thus reducing latency in the data transfer process. Moreover, the data format allows for optimization of how the object data is prioritized and interleaved to achieve desired performance objectives upon delivery of the multimedia objects.

Abstract: A noise canceling circuit is provided in a dynamic circuit that includes a high fan-in domino gate. The noise canceling circuit decouples noise from neighboring wires in the dynamic circuit that is injected into a wire that controls the domino gate.

Abstract: A transition encoded dynamic bus includes an encoder circuit at the input to the bus and a decoder circuit at the output to the bus. The encoder circuit generates a signal indicative of a transition at the input to the bus rather than the actual value at the input. The decoder circuit decodes the transition encoded information to track the appropriate value to be output from the bus.