Patents by Inventor Mark Bohr

Mark Bohr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8174060
    Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: May 8, 2012
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
  • Patent number: 8154067
    Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: April 10, 2012
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
  • Publication number: 20110157854
    Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.
    Type: Application
    Filed: March 4, 2011
    Publication date: June 30, 2011
    Inventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
  • Patent number: 7951673
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: May 31, 2011
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • Patent number: 7952194
    Abstract: A voltage regulation module and system for an integrated circuit die. The voltage regulation module includes an interposer situated in a stack between a substrate and the integrated circuit die. The interposer includes a hybrid array of voltage regulation elements for receiving voltage from the power supply and for down-converting the voltage from the power supply into a regulated voltage supplied to the integrated circuit die. The hybrid array of voltage regulation elements includes both high-bandwidth linear regulation elements for providing voltage regulation to areas on the integrated circuit die that intermittently demand relatively high current levels, and low-bandwidth switching regulator elements that are highly power efficient.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: May 31, 2011
    Assignee: Intel Corporation
    Inventors: Raj Nair, Johanna Swan, Bala Natarajan, Mark Bohr
  • Publication number: 20110084387
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Application
    Filed: December 20, 2010
    Publication date: April 14, 2011
    Inventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
  • Patent number: 7919859
    Abstract: Embodiments of the invention include apparatuses and methods relating to copper die bumps with electtomigration cap and plated solder. In one embodiment, an apparatus comprises an integrated circuit die, a plurality of copper bumps on a surface of the die, electromigration(EM) caps substantially covering a mating surface of the copper bumps capable of controlling intermetallic formation between the cooper bumps and solder, and solder plating on the EM caps capable of protecting the EM caps from oxidation prior to packaging.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: April 5, 2011
    Assignee: Intel Corporation
    Inventors: Ting Zhong, Val Dubin, Mark Bohr
  • Patent number: 7755082
    Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: July 13, 2010
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Swaminathan Sivakumar, Andrew A. Berlin, Mark Bohr
  • Publication number: 20100151669
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Application
    Filed: February 26, 2010
    Publication date: June 17, 2010
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • Patent number: 7704833
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • Patent number: 7679145
    Abstract: A semiconductor substrate having metal oxide semiconductor (MOS) devices, such as an integrated circuit die, is mechanically coupled to a stress structure to apply a stress that improves the performance of at least a portion of the MOS devices on the die.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: March 16, 2010
    Assignee: Intel Corporation
    Inventors: Jun He, Zhiyong Ma, Jose A. Maiz, Mark Bohr, Martin D. Giles, Guanghai Xu
  • Patent number: 7662674
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: February 16, 2010
    Assignee: Intel Corporation
    Inventors: Jose A. Maiz, Jun He, Mark Bohr
  • Publication number: 20090189193
    Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.
    Type: Application
    Filed: April 6, 2009
    Publication date: July 30, 2009
    Applicant: INTEL CORPORATION
    Inventors: GIUSEPPE CURELLO, Ian R. Post, Chia-Hong Jan, Mark Bohr
  • Patent number: 7560780
    Abstract: A semiconductor device and method for its fabrication are described. An active region spacer may be formed on a top surface of an isolation region and adjacent to a sidewall of an active region. In one embodiment, the active region spacer may suppress the formation of metal pipes in the active region.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: July 14, 2009
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Sunit Tyagi, Mark Bohr
  • Patent number: 7541239
    Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 2, 2009
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
  • Patent number: 7524754
    Abstract: In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated circuit and package substrate. The shunt provides a third electric current pathway between the first bump and the second bump.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: April 28, 2009
    Assignee: Intel Corporation
    Inventors: Mark Bohr, Jun He, Fay Hua, Dustin P. Wood
  • Patent number: 7510927
    Abstract: The present invention discloses a method including: providing a substrate; forming a buried oxide layer over the substrate; forming a thin silicon body layer over the buried oxide layer, the thin silicon body layer having a thickness of 3-40 nanometers; forming a pad oxide layer over the thin silicon body layer; forming a silicon nitride layer over the pad oxide layer; forming a photoresist over the silicon nitride layer; forming an opening in the photoresist; removing the silicon nitride layer in the opening; partially or completely removing the pad oxide layer in the opening; removing the photoresist over the silicon nitride layer; forming a field oxide layer from the thin silicon body layer in the opening; removing the silicon nitride layer over the pad oxide layer; and removing the pad oxide layer over the thin silicon body layer.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: March 31, 2009
    Assignee: Intel Corporation
    Inventors: Mark Bohr, Julie Tsai
  • Patent number: 7491988
    Abstract: A semiconductor transistor structure with increased mobility in the channel zone and a method of its fabrication are described. A semiconductor substrate having a first dopant is formed. A diffusion barrier layer having a second dopant is formed on the semiconductor substrate to suppress outdiffusion of the first dopant. Next, a semiconductor layer having substantially low dopant concentration relative to the first layer is epitaxially grown on the diffusion barrier layer. The semiconductor layer defines a channel in the semiconductor transistor structure. The low dopant concentration in the semiconductor layer increases the mobility of the carriers in the channel of the semiconductor transistor structure. A gate electrode and a gate dielectric are formed on the semiconductor layer with the low dopant concentration.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: February 17, 2009
    Assignee: Intel Corporation
    Inventors: Peter G. Tolchinsky, Mark Bohr, Irwin Yablok
  • Patent number: 7470620
    Abstract: Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: December 30, 2008
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Mark Bohr
  • Publication number: 20080230896
    Abstract: Embodiments of the invention include apparatuses and methods relating to copper die bumps with electromigration cap and plated solder. In one embodiment, an apparatus comprises an integrated circuit die, a plurality of copper bumps on a surface of the die, electromigration (EM) caps substantially covering a mating surface of the copper bumps capable of controlling intermetallic formation between the copper bumps and a solder, and solder plating on the EM caps capable of protecting the EM caps from oxidation prior to packaging.
    Type: Application
    Filed: March 23, 2007
    Publication date: September 25, 2008
    Inventors: Ting Zhong, Val Dubin, Mark Bohr