Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET.

Abstract: An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a buried insulator having at least two layers. A body is formed from the semiconductor layer situated between the recesses, and the body comprises a top body surface and a bottom body surface that define a body thickness. Top portions of the S/D structures are within and abut the body thickness. An improved method for forming the improved transistor structure is also described and comprises: forming recesses through a semiconductor layer and a first layer of a buried insulator so that a body is situated between the recesses; and forming S/D structures into the recesses so that top portions of the S/D structures are within and abut a body thickness.

Abstract: An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a buried insulator having at least two layers. A body is formed from the semiconductor layer situated between the recesses, and the body comprises a top body surface and a bottom body surface that define a body thickness. Top portions of the S/D structures are within and abut the body thickness. An improved method for forming the improved transistor structure is also described and comprises: forming recesses through a semiconductor layer and a first layer of a buried insulator so that a body is situated between the recesses; and forming S/D structures into the recesses so that top portions of the S/D structures are within and abut a body thickness.

Abstract: A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

Abstract: A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

Abstract: A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.