Patents by Inventor Mark D. Jaffe
Mark D. Jaffe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20090237103Abstract: A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.Type: ApplicationFiled: March 20, 2008Publication date: September 24, 2009Applicant: International Business Machines CorporationInventors: John J. Ellis-Monaghan, Mark D. Jaffe, Sambasivan Narayan, Anthony J. Perri, Richard J. Rassel, Tian Xia
-
Publication number: 20090224349Abstract: An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.Type: ApplicationFiled: April 14, 2009Publication date: September 10, 2009Applicant: International Business Machines CorporationInventors: Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Richard J. Rassel
-
Patent number: 7586139Abstract: An imaging sensor with an array of FET pixels and method of forming the imaging sensor. Each pixel is a semiconductor island, e.g., N-type silicon on a Silicon on insulator (SOI) wafer. FETs are formed in one photodiode electrode, e.g., a P-well cathode. A color filter may be attached to an opposite surface of island. A protective layer (e.g., glass or quartz) or window is fixed to the pixel array at the color filters. The image sensor may be illuminated from the backside with cell wiring above the cell. So, an optical signal passes through the protective layer is filtered by the color filters and selectively sensed by a corresponding photo-sensor.Type: GrantFiled: February 17, 2006Date of Patent: September 8, 2009Assignee: International Business Machines CorporationInventors: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Alan Loiseau, Richard J. Rassel
-
Patent number: 7572701Abstract: A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. A portion of the bottom of the gate conductor is recessed below the surface of the substrate.Type: GrantFiled: April 13, 2007Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: James W. Adkisson, John Ellis-Monaghan, Mark D. Jaffe, Jerome B. Lasky
-
Patent number: 7563636Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.Type: GrantFiled: July 14, 2008Date of Patent: July 21, 2009Assignee: International Business Machines CorporationInventors: James W. Adkisson, Andres Bryant, John J. Ellis-Monaghan, Mark D. Jaffe, Jeffrey B. Johnson, Alain Loiseau
-
Patent number: 7537951Abstract: An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.Type: GrantFiled: November 15, 2006Date of Patent: May 26, 2009Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Richard J. Rassel
-
Patent number: 7538373Abstract: An imaging circuit, an imaging sensor, and a method of imaging. The imaging cell circuit including one or more imaging cell circuits, each imaging cell circuit comprising: a transistor having a floating body for holding charge generated in the floating body in response to exposure of the floating body to electromagnetic radiation; means for biasing the transistor wherein an output of the transistor is responsive to the electromagnetic radiation; and means for selectively connecting the floating body to a reset voltage supply.Type: GrantFiled: June 20, 2007Date of Patent: May 26, 2009Assignee: International Business Machines CorporationInventors: John J. Ellis-Monaghan, Mark D. Jaffe, Alain Loiseau
-
Publication number: 20090124047Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.Type: ApplicationFiled: January 14, 2009Publication date: May 14, 2009Inventors: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Stephen E. Luce, Richard J. Rassel, Edmund J. Sprogis
-
Patent number: 7531392Abstract: The present invention relates to semiconductor-on-insulator (SOI) substrate structures that contain surface semiconductor regions of different crystal orientations located directly on an insulator layer. The present invention also relates to methods for fabricating such SOI substrate structures, by growing an insulator layer directly on a multi-orientation bulk semiconductor substrate that comprises surface semiconductor regions of different crystal orientations located directly on a semiconductor base layer, and removing the semiconductor base layer, thereby forming a multi-orientation SOI substrate structure that comprises surface semiconductor regions of different crystal orientations located directly on the insulator layer.Type: GrantFiled: February 27, 2006Date of Patent: May 12, 2009Assignee: International Business Machines CorporationInventors: John J. Ellis-Monaghan, Mark D. Jaffe
-
Patent number: 7521798Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.Type: GrantFiled: November 20, 2007Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Stephen E. Luce, Richard J. Rassel, Edmund J. Sprogis
-
Patent number: 7517806Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET.Type: GrantFiled: July 21, 2005Date of Patent: April 14, 2009Assignee: International Business Machines CorporationInventors: Andres Bryant, William F. Clark, Jr., David M. Fried, Mark D. Jaffe, Edward J. Nowak, John J. Pekarik, Christopher S. Putnam
-
Publication number: 20090085152Abstract: Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.Type: ApplicationFiled: October 1, 2007Publication date: April 2, 2009Inventors: Kerry Bernstein, Timothy J. Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Stephen E. Luce, Anthony K. Stamper
-
Publication number: 20090045502Abstract: A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate.Type: ApplicationFiled: August 15, 2007Publication date: February 19, 2009Inventors: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Edmund J. Sprogis
-
Patent number: 7491992Abstract: A structure (and method for forming the same) for an image sensor cell. The method includes providing a semiconductor substrate. Then, a charge collection well is formed in the semiconductor substrate, the charge collection well comprising dopants of a first doping polarity. Next, a surface pinning layer is formed in the charge collection well, the surface pinning layer comprising dopants of a second doping polarity opposite to the first doping polarity. Then, an electrically conductive push electrode is formed in direct physical contact with the surface pinning layer but not in direct physical contact with the charge collection well. Then, a transfer transistor is formed on the semiconductor substrate. The transfer transistor includes first and second source/drain regions and a channel region. The first and second source/drain regions comprise dopants of the first doping polarity. The first source/drain region is in direct physical contact with the charge collection well.Type: GrantFiled: January 2, 2007Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: James W. Adkisson, John J. Ellis-Monaghan, Mark D. Jaffe, Richard J. Rassel, Jeffrey P. Gambino
-
Patent number: 7491561Abstract: A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation structure is formed adjacent to the photosensitive device pinning layer. The trench isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the trench are driven into the underlying substrate during an anneal.Type: GrantFiled: November 27, 2006Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: James W. Adkisson, Mark D. Jaffe, Robert K. Leidy
-
Publication number: 20090001427Abstract: A pixel sensor structure, method of manufacture and method of operating. Disclosed is a buffer pixel cell comprising a barrier region for preventing stray charge carriers from arriving at a dark current correction pixel cell. The buffer pixel cell is located in the vicinity of the dark current correction pixel cell and the buffer pixel cell resembles an active pixel cell. Thus, an environment surrounding the dark current correction pixel cell is similar to the environment surrounding an active pixel cell.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Inventors: James W. Adkisson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe
-
Publication number: 20080296476Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.Type: ApplicationFiled: July 14, 2008Publication date: December 4, 2008Inventors: James W. Adkisson, Andres Bryant, John J. Ellis-Monaghan, Mark D. Jaffe, Jeffrey B. Johnson, Alain Lolseau
-
Patent number: 7459360Abstract: A method of forming a pixel sensor cell structure. The method of forming the pixel cell comprises forming a doped layer adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.Type: GrantFiled: March 2, 2007Date of Patent: December 2, 2008Assignee: International Business Machines CorporationInventors: James W. Adkisson, Andres Bryant, John Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Jerome B. Lasky, Richard A. Phelps
-
Publication number: 20080274578Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.Type: ApplicationFiled: July 14, 2008Publication date: November 6, 2008Inventors: James W. Adkisson, Andres Bryant, John J. Ellis-Monaghan, Mark D. Jaffe, Jeffrey B. Johnson, Alain Loiseau
-
Publication number: 20080272400Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.Type: ApplicationFiled: July 14, 2008Publication date: November 6, 2008Inventors: James W. Adkisson, Andres Bryant, John J. Ellis-Monaghan, Mark D. Jaffe, Jeffrey B. Johnson, Alain Loiseau