Abstract: The present invention provides a light shield for shielding the floating diffusion of a complementary metal-oxide semiconductor (CMOS) imager. In accordance with an embodiment of the present invention, there is provided a pixel sensor cell including: a device region formed on a substrate; and a first layer of material forming a sidewall adjacent to a side of the device region for blocking electromagnetic radiation from the device region.

Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.

Abstract: An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

Abstract: The image quality of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image quality may be improved by accounting for time dependent changes in the output of dark pixels in dark pixel rows or dark pixel columns. In addition, voltage and time dependent changes in the output of dark pixels may also be measured to provide an accurate estimate of the noise introduced to the charge held in the floating drains. Such methods may be employed individually or in combination to improve the quality of the image.

Abstract: A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.

Abstract: A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

Abstract: An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.

Abstract: An imaging sensor with an array of FET pixels and method of forming the imaging sensor. Each pixel is a semiconductor island, e.g., N-type silicon on a Silicon on insulator (SOI) wafer. FETs are formed in one photodiode electrode, e.g., a P-well cathode. A color filter may be attached to an opposite surface of island. A protective layer (e.g., glass or quartz) or window is fixed to the pixel array at the color filters. The image sensor may be illuminated from the backside with cell wiring above the cell. So, an optical signal passes through the protective layer is filtered by the color filters and selectively sensed by a corresponding photo-sensor.

Abstract: A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. A portion of the bottom of the gate conductor is recessed below the surface of the substrate.

Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

Abstract: An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.

Abstract: An imaging circuit, an imaging sensor, and a method of imaging. The imaging cell circuit including one or more imaging cell circuits, each imaging cell circuit comprising: a transistor having a floating body for holding charge generated in the floating body in response to exposure of the floating body to electromagnetic radiation; means for biasing the transistor wherein an output of the transistor is responsive to the electromagnetic radiation; and means for selectively connecting the floating body to a reset voltage supply.

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract: The present invention relates to semiconductor-on-insulator (SOI) substrate structures that contain surface semiconductor regions of different crystal orientations located directly on an insulator layer. The present invention also relates to methods for fabricating such SOI substrate structures, by growing an insulator layer directly on a multi-orientation bulk semiconductor substrate that comprises surface semiconductor regions of different crystal orientations located directly on a semiconductor base layer, and removing the semiconductor base layer, thereby forming a multi-orientation SOI substrate structure that comprises surface semiconductor regions of different crystal orientations located directly on the insulator layer.

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET.

Abstract: Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.

Abstract: A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate.

Abstract: A structure (and method for forming the same) for an image sensor cell. The method includes providing a semiconductor substrate. Then, a charge collection well is formed in the semiconductor substrate, the charge collection well comprising dopants of a first doping polarity. Next, a surface pinning layer is formed in the charge collection well, the surface pinning layer comprising dopants of a second doping polarity opposite to the first doping polarity. Then, an electrically conductive push electrode is formed in direct physical contact with the surface pinning layer but not in direct physical contact with the charge collection well. Then, a transfer transistor is formed on the semiconductor substrate. The transfer transistor includes first and second source/drain regions and a channel region. The first and second source/drain regions comprise dopants of the first doping polarity. The first source/drain region is in direct physical contact with the charge collection well.