Patents by Inventor Mark D. Jaffe
Mark D. Jaffe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10224280Abstract: A back-side device structure with a silicon-on-insulator substrate that includes: a first dielectric layer that includes a first via that communicates with a trench, a contact plug that fills the trench, and a first contact formed in a second dielectric layer. The first contact fills the first via and connects with the contact plug and a wire formed in a third dielectric layer. A final substrate is connected to a buried insulator layer of the silicon-on-insulator substrate such that the contact plug contacts metallization of the final substrate.Type: GrantFiled: November 28, 2017Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
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Patent number: 10211087Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.Type: GrantFiled: November 14, 2017Date of Patent: February 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark D. Jaffe, Alvin J. Joseph, Qizhi Liu, Anthony K. Stamper
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Patent number: 10211146Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.Type: GrantFiled: May 12, 2016Date of Patent: February 19, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Zhong-Xiang He, Mark D. Jaffe, Randy L. Wolf, Alvin J. Joseph, Brett T. Cucci, Anthony K. Stamper
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Patent number: 10191213Abstract: Methods and structures for shielding optical waveguides are provided. A method includes forming a first optical waveguide core and forming a second optical waveguide core adjacent to the first optical waveguide core. The method also includes forming an insulator layer over the first optical waveguide core and the second optical waveguide core. The method further includes forming a shielding structure in the insulator layer between the first optical waveguide core and the second optical waveguide core.Type: GrantFiled: January 9, 2014Date of Patent: January 29, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson, Jed H. Rankin
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Publication number: 20190019914Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.Type: ApplicationFiled: September 20, 2018Publication date: January 17, 2019Inventors: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON
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Patent number: 10170418Abstract: A method for fabricating a backside device contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer, includes forming a trench in the device layer. A trench is formed in the device layer. A sacrificial plug is formed in the trench. The handle wafer is removed to reveal the buried insulator layer. The buried insulator layer is partially removed to expose the sacrificial plug at a bottom of the trench. The sacrificial plug is removed. Backside processing of the buried insulator layer is performed. The trench is filled with a conductor to form a contact plug. A final substrate is connected to the buried insulator layer such that the contact plug contacts metallization of the final substrate.Type: GrantFiled: November 28, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
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Patent number: 10164596Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes.Type: GrantFiled: August 30, 2017Date of Patent: December 25, 2018Assignee: SMARTSENS TECHNOLOGY (CAYMAN) CO., LTD.Inventors: James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Mark D. Jaffe, Anthony K. Stamper, Randy L. Wolf
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Patent number: 10164597Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes.Type: GrantFiled: August 30, 2017Date of Patent: December 25, 2018Assignee: SMARTSENS TECHNOLOGY (CAYMAN) CO., LTD.Inventors: James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Mark D. Jaffe, Anthony K. Stamper, Randy L. Wolf
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Patent number: 10164101Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with improved channel mobility and methods of manufacture. A structure includes: a curved beam structure formed from at least one stressed material; a cavity below the curved beam structure; and at least one semiconductor device on a top portion or a bottom portion of the curved beam structure whose carrier mobility is increased or decreased by a curvature of the curved beam structure.Type: GrantFiled: October 23, 2017Date of Patent: December 25, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Renata A. Camillo-Castillo, Anthony K. Stamper, Vibhor Jain, Mark D. Jaffe
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Patent number: 10157838Abstract: A method for fabricating a backside device contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer, includes forming a trench in the device layer. The trench is filled with a contact plug. The backside device contact includes the contact plug. After the trench is filled with the contact plug, the handle wafer is removed to reveal the buried insulator layer. The buried insulator layer is partially removed to expose the trench containing the contact plug. A final substrate is connected to the buried insulator layer such that the contact plug contacts metallization of the final substrate. A device structure is formed using the device layer.Type: GrantFiled: November 28, 2017Date of Patent: December 18, 2018Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
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Patent number: 10157777Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.Type: GrantFiled: May 12, 2016Date of Patent: December 18, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Zhong-Xiang He, Mark D. Jaffe, Randy L. Wolf, Alvin J. Joseph, Brett T. Cucci, Anthony K. Stamper
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Patent number: 10141472Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.Type: GrantFiled: January 17, 2017Date of Patent: November 27, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson
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Publication number: 20180286748Abstract: A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed within a device layer of the silicon-on-insulator substrate and between a buried insulator layer of the silicon on-insulator substrate and a dielectric layer disposed above and coupled to the device layer. An electrically-conducting connection is located in a first trench extending from the device layer through the buried insulator layer to a trap-rich layer such that the electrically-conducting connection is coupled with a substrate.Type: ApplicationFiled: May 31, 2018Publication date: October 4, 2018Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
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Publication number: 20180269348Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.Type: ApplicationFiled: May 16, 2018Publication date: September 20, 2018Inventors: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON
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Patent number: 10079248Abstract: Device structures for a field-effect transistor with a body contact and methods of forming such device structures. An opening is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate and into a buried oxide layer of the silicon-on-insulator substrate. The buried oxide layer is laterally etched at the location of the opening to define a cavity in the buried oxide layer. The cavity is located partially beneath a section of the device layer, and the cavity is filled with a semiconductor material to form a body contact. A well is formed in the section of the device layer, and the body contact is coupled with a portion of the well.Type: GrantFiled: November 18, 2016Date of Patent: September 18, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Steven M. Shank, Mark D. Jaffe, John J. Pekarik
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Patent number: 10074561Abstract: A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed using a device layer of the silicon-on-insulator substrate. A trap-rich layer is between a substrate and a buried insulator layer of the silicon on-insulator substrate. An electrically-conducting connection is located in a trench extending from the device layer through the buried insulator layer to the trap-rich layer such that the electrically-conducting connection is coupled with the substrate. The electrically-conducting connection at least partially comprised of trap-rich material.Type: GrantFiled: September 23, 2016Date of Patent: September 11, 2018Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
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Publication number: 20180254761Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes.Type: ApplicationFiled: May 4, 2018Publication date: September 6, 2018Inventors: James W. ADKISSON, Panglijen CANDRA, Thomas J. DUNBAR, Mark D. JAFFE, Anthony K. STAMPER, Randy L. WOLF
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Publication number: 20180254374Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.Type: ApplicationFiled: May 4, 2018Publication date: September 6, 2018Inventors: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON
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Patent number: 10050171Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.Type: GrantFiled: January 17, 2017Date of Patent: August 14, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson
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Patent number: 10037911Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.Type: GrantFiled: August 31, 2017Date of Patent: July 31, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Anthony K. Stamper, Mukta G. Farooq, John A. Fitzsimmons, Mark D. Jaffe, Randy L. Wolf