Patents by Inventor Mark D. Jaffe

Mark D. Jaffe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing switchable filters
    Patent number: 9048809
    Abstract: Switchable and/or tunable filters and methods of manufacture. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam formed above the piezoelectric substrate and at a location in which, upon actuation, the MEMS beam shorts the piezoelectric filter structure by contacting at least one of the plurality of electrodes.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: June 2, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Jeffrey P. Gambino, Mark D. Jaffe, Anthony K. Stamper, Randy L. Wolf
  • Vertically curved waveguide
    Patent number: 9002156
    Abstract: An optical waveguide structure may include an optical waveguide structure located within a semiconductor structure and an optical coupler. The optical coupler may include a metallic structure located within an electrical interconnection region of the semiconductor structure, whereby the metallic structure extends downward in a substantially curved shape from a top surface of the electrical interconnection region and couples to the optical waveguide structure. The optical coupler may further include an optical signal guiding region bounded within the metallic structure, whereby the optical coupler receives an optical signal from the top surface and couples the optical signal to the optical waveguide structure such that the optical signal propagation is substantially vertical at the top surface and substantially horizontal at the optical waveguide structure.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson, Jed H. Rankin
  • Segmented guard ring structures with electrically insulated gap structures and design structures thereof
    Patent number: 8987067
    Abstract: Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes forming diffusion regions to electrically insulate a gap in a substrate formed by segmented portions of the guard ring structure.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Barry, Phillip F. Chapman, Jeffrey P. Gambino, Michael L. Gautsch, Mark D. Jaffe, Kevin N. Ogg, Bradley A. Orner
  • HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS
    Publication number: 20150072504
    Abstract: According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.
    Type: Application
    Filed: November 18, 2014
    Publication date: March 12, 2015
    Inventors: Alan B. Botula, Jeffrey E. Hanrahan, Mark D. Jaffe, Alvin J. Joseph, Dale W. Martin, Gerd Pfeiffer, James A. Slinkman
  • High resistivity silicon-on-insulator substrate and method of forming
    Patent number: 8963293
    Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph
  • High linearity SOI wafer for low-distortion circuit applications
    Patent number: 8951896
    Abstract: According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Jeffrey E. Hanrahan, Mark D. Jaffe, Alvin J. Joseph, Dale W. Martin, Gerd Pfeiffer, James A. Slinkman
  • THIN BODY SWITCH TRANSISTOR
    Publication number: 20150001622
    Abstract: An integrated recessed thin body field effect transistor (FET) and methods of manufacture are disclosed. The method includes recessing a portion of a semiconductor material. The method further includes forming at least one gate structure within the recessed portion of the semiconductor material.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventors: Michel J. Abou-Khalil, Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, James A. Slinkman
  • HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS
    Publication number: 20150004778
    Abstract: According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: ALAN B. BOTULA, Jeffrey E. Hanrahan, Mark D. Jaffe, Alvin J. Joseph, Dale W. Martin, Gerd Pfeiffer, James A. Slinkman
  • Method of manufacturing a film bulk acoustic resonator with a loading element
    Patent number: 8910355
    Abstract: Manufacturing a semiconductor structure including modifying a frequency of a Film Bulk Acoustic Resonator (FBAR) device though a vent hole of a sealing layer surrounding the FBAR device.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Jeffrey P. Gambino, Mark D. Jaffe, Anthony K. Stamper, Randy L. Wolf
  • Vertical bend waveguide coupler for photonics applications
    Patent number: 8903210
    Abstract: An optical waveguide structure may include a dielectric layer having a top surface, an optical waveguide structure, and an optical coupler embedded within the dielectric layer. The optical coupler may have both a substantially vertical portion that couples to the top surface of the dielectric layer and a substantially horizontal portion that couples to the optical waveguide structure. The substantially vertical portion and the substantially horizontal portion are separated by a curved portion.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson, Jed H. Rankin
  • VERTICALLY CURVED WAVEGUIDE
    Publication number: 20140321802
    Abstract: An optical waveguide structure may include an optical waveguide structure located within a semiconductor structure and an optical coupler. The optical coupler may include a metallic structure located within an electrical interconnection region of the semiconductor structure, whereby the metallic structure extends downward in a substantially curved shape from a top surface of the electrical interconnection region and couples to the optical waveguide structure. The optical coupler may further include an optical signal guiding region bounded within the metallic structure, whereby the optical coupler receives an optical signal from the top surface and couples the optical signal to the optical waveguide structure such that the optical signal propagation is substantially vertical at the top surface and substantially horizontal at the optical waveguide structure.
    Type: Application
    Filed: April 29, 2013
    Publication date: October 30, 2014
    Applicant: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson, Jed H. Rankin
  • VERTICAL BEND WAVEGUIDE COUPLER FOR PHOTONICS APPLICATIONS
    Publication number: 20140321801
    Abstract: An optical waveguide structure may include a dielectric layer having a top surface, an optical waveguide structure, and an optical coupler embedded within the dielectric layer. The optical coupler may have both a substantially vertical portion that couples to the top surface of the dielectric layer and a substantially horizontal portion that couples to the optical waveguide structure. The substantially vertical portion and the substantially horizontal portion are separated by a curved portion.
    Type: Application
    Filed: April 29, 2013
    Publication date: October 30, 2014
    Applicant: International Business Machnes Corporation
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson, Jed H. Rankin
  • COMPENSATION FOR A CHARGE IN A SILICON SUBSTRATE
    Publication number: 20140306325
    Abstract: A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer.
    Type: Application
    Filed: June 24, 2014
    Publication date: October 16, 2014
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, Richard A. Phelps, James Slinkman, Randy L. Wolf
  • Compensation for a charge in a silicon substrate
    Patent number: 8828746
    Abstract: A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, Richard A. Phelps, James Slinkman, Randy L. Wolf
  • SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STRUCTURES AND DESIGN STRUCTURES THEREOF
    Publication number: 20140246752
    Abstract: Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes forming diffusion regions to electrically insulate a gap in a substrate formed by segmented portions of the guard ring structure.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Barry, Phillip F. Chapman, Jeffrey P. Gambino, Michael L. Gautsch, Mark D. Jaffe, Kevin N. Ogg, Bradley A. Orner
  • Diffusion barrier for oppositely doped portions of gate conductor
    Patent number: 8796130
    Abstract: A method patterns a polysilicon gate over two immediately adjacent, opposite polarity transistor devices. The method patterns a mask over the polysilicon gate. The mask has an opening in a location where the opposite polarity transistor devices abut one another. The method then removes some (a portion) of the polysilicon gate through the opening to form at least a partial recess (or potentially a complete opening) in the polysilicon gate. The recess separates the polysilicon gate into a first polysilicon gate and a second polysilicon gate. After forming the recess, the method dopes the first polysilicon gate using a first polarity dopant and dopes the second polysilicon gate using a second polarity dopant having an opposite polarity of the first polarity dopant.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Russell T. Herrin, Mark D. Jaffe, Laura J. Schutz
  • Isolation structures for global shutter imager pixel, methods of manufacture and design structures
    Patent number: 8796057
    Abstract: Pixel sensor cells, e.g., CMOS optical imagers, methods of manufacturing and design structures are provided with isolation structures that prevent carrier drift to diffusion regions. The pixel sensor cell includes a photosensitive region and a gate adjacent to the photosensitive region. The pixel sensor cell further includes a diffusion region adjacent to the gate. The pixel sensor cell further includes an isolation region located below a channel region of the gate and about the photosensitive region, which prevents electrons collected in the photosensitive region to drift to the diffusion region.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Mark D. Jaffe
  • High resistivity silicon-on-insulator substrate and method of forming
    Patent number: 8741739
    Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph
  • Discontinuous guard ring
    Patent number: 8729664
    Abstract: An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: May 20, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Mark D. Levy, John C. Malinowski
  • COMPENSATION FOR A CHARGE IN A SILICON SUBSTRATE
    Publication number: 20140131800
    Abstract: A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer.
    Type: Application
    Filed: November 14, 2012
    Publication date: May 15, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, Richard A. Phelps, James Slinkman, Randy L. Wolf