Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

Abstract: Various particular embodiments include an optical structure, including: a photonic microring including an integral signal detector for detecting a level of an optical signal in the photonic microring; and a controller, coupled to the signal detector, for selectively adjusting a resonant frequency of the photonic microring based on the detected level of the optical signal in the photonic microring.

Abstract: Approaches for an on-chip antenna are provided. A method includes forming an antenna in an insulator layer at a front side of a substrate. The method also includes forming a trench in the substrate underneath the antenna. The method further includes forming a fill material in the trench. The substrate is composed of a material having a first dielectric constant. The fill material has a second dielectric constant that is less than the first dielectric constant.

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

Abstract: Chip structures that include distributed wiring layouts and fabrication methods for forming such chip structures. A device structure is formed that includes a plurality of first device regions and a plurality of second device regions. A first wiring level is formed that includes a first wire coupled with the first device regions. A second wiring level is formed that includes a second wire coupled with the second device regions. The first wiring level is vertically separated from the second wiring level by a buried oxide layer of the silicon-on-insulator substrate.

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

Abstract: Various particular embodiments include an optical structure, including: a photonic microring including an integral signal detector for detecting a level of an optical signal in the photonic microring; and a controller, coupled to the signal detector, for selectively adjusting a resonant frequency of the photonic microring based on the detected level of the optical signal in the photonic microring.

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

Abstract: Device structures and fabrication methods for a backside contact to a final substrate. An electrically-conducting connection is formed that extends through a device layer of a silicon-on-insulator substrate and partially through a buried insulator layer of the silicon-on-insulator substrate. After the electrically-conducting connection is formed, a handle wafer of the silicon-on-insulator substrate is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is coupled to the buried insulator layer such that the electrically-conducting connection is coupled with the final substrate.

Abstract: A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed using a device layer of the silicon-on-insulator substrate. A trap-rich layer is between a substrate and a buried insulator layer of the silicon on-insulator substrate. An electrically-conducting connection is located in a trench extending from the device layer through the buried insulator layer to the trap-rich layer such that the electrically-conducting connection is coupled with the substrate. The electrically-conducting connection at least partially comprised of trap-rich material.

Abstract: CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate.

Abstract: A back-side device structure with a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, a trench that extends through the device layer and that partially extends through the buried insulator layer, at least one dielectric layer that is formed on the device layer and includes a first opening that communicates with the trench and a contact plug that fills the trench. A final substrate is connected to the buried insulator layer such that the contact plug contacts metallization of the final substrate. The contact plug is externally connected with a source to provide signals to the back-side device structure through a wire formed in the at least one dielectric layer.

Abstract: Device structures and fabrication methods for a backside contact to a final substrate An electrically-conducting connection is formed that extends through a device layer of a silicon-on-insulator substrate and partially through a buried insulator layer of the silicon-on-insulator substrate. After the electrically-conducting connection is formed, a handle wafer of the silicon-on-insulator substrate is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is coupled to the buried insulator layer such that the electrically-conducting connection is coupled with the final substrate.

Abstract: Device structures and fabrication methods for a backside contact to a final substrate An electrically-conducting connection is formed that extends through a device layer of a silicon-on-insulator substrate and partially through a buried insulator layer of the silicon-on-insulator substrate. After the electrically-conducting connection is formed, a handle wafer of the silicon-on-insulator substrate is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is coupled to the buried insulator layer such that the electrically-conducting connection is coupled with the final substrate.