Patents by Inventor Mark D. Jaffe

Mark D. Jaffe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Compensation for a charge in a silicon substrate
    Patent number: 8828746
    Abstract: A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, Richard A. Phelps, James Slinkman, Randy L. Wolf
  • SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STRUCTURES AND DESIGN STRUCTURES THEREOF
    Publication number: 20140246752
    Abstract: Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes forming diffusion regions to electrically insulate a gap in a substrate formed by segmented portions of the guard ring structure.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Barry, Phillip F. Chapman, Jeffrey P. Gambino, Michael L. Gautsch, Mark D. Jaffe, Kevin N. Ogg, Bradley A. Orner
  • Diffusion barrier for oppositely doped portions of gate conductor
    Patent number: 8796130
    Abstract: A method patterns a polysilicon gate over two immediately adjacent, opposite polarity transistor devices. The method patterns a mask over the polysilicon gate. The mask has an opening in a location where the opposite polarity transistor devices abut one another. The method then removes some (a portion) of the polysilicon gate through the opening to form at least a partial recess (or potentially a complete opening) in the polysilicon gate. The recess separates the polysilicon gate into a first polysilicon gate and a second polysilicon gate. After forming the recess, the method dopes the first polysilicon gate using a first polarity dopant and dopes the second polysilicon gate using a second polarity dopant having an opposite polarity of the first polarity dopant.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Russell T. Herrin, Mark D. Jaffe, Laura J. Schutz
  • Isolation structures for global shutter imager pixel, methods of manufacture and design structures
    Patent number: 8796057
    Abstract: Pixel sensor cells, e.g., CMOS optical imagers, methods of manufacturing and design structures are provided with isolation structures that prevent carrier drift to diffusion regions. The pixel sensor cell includes a photosensitive region and a gate adjacent to the photosensitive region. The pixel sensor cell further includes a diffusion region adjacent to the gate. The pixel sensor cell further includes an isolation region located below a channel region of the gate and about the photosensitive region, which prevents electrons collected in the photosensitive region to drift to the diffusion region.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Mark D. Jaffe
  • High resistivity silicon-on-insulator substrate and method of forming
    Patent number: 8741739
    Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph
  • Discontinuous guard ring
    Patent number: 8729664
    Abstract: An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: May 20, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Mark D. Levy, John C. Malinowski
  • COMPENSATION FOR A CHARGE IN A SILICON SUBSTRATE
    Publication number: 20140131800
    Abstract: A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer.
    Type: Application
    Filed: November 14, 2012
    Publication date: May 15, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, Richard A. Phelps, James Slinkman, Randy L. Wolf
  • Saw filter having planar barrier layer and method of making
    Patent number: 8723392
    Abstract: Disclosed herein is a surface acoustic wave (SAW) filter and method of making the same. The SAW filter includes a piezoelectric substrate; a planar barrier layer disposed above the piezoelectric substrate, and at least one conductor buried in the piezoelectric substrate and the planar barrier layer.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Jeffrey P. Gambino, Mark D. Jaffe, Anthony K. Stamper, Randy L. Wolf
  • HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING
    Publication number: 20140124902
    Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.
    Type: Application
    Filed: January 9, 2014
    Publication date: May 8, 2014
    Applicant: International Business Machines Corporation
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph
  • Double-sided integrated circuit chips
    Patent number: 8689152
    Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Timothy Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Paul D. Kartschoke, Stephen E. Luce, Anthony K. Stamper
  • Methods for enhancing quality of pixel sensor image frames for global shutter imaging
    Patent number: 8681254
    Abstract: The image qualify of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image quality may be improved by accounting for time dependent changes in the output of dark pixels in dark pixel rows or dark pixel columns. In addition, voltage and time dependent changes in the output of dark pixels may also be measured to provide an accurate estimate of the noise introduced to the charge held in the floating drains. Such methods may be employed individually or in combination to improve the quality of the image.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Mark D. Jaffe
  • Anti-blooming pixel sensor cell with active neutral density filter, methods of manufacture, and design structure
    Patent number: 8618588
    Abstract: A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kristin M. Ackerson, Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Richard J. Rassel, Robert M. Rassel
  • DISCONTINUOUS GUARD RING
    Publication number: 20130256826
    Abstract: An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.
    Type: Application
    Filed: April 2, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Mark D. Levy, John C. Malinowski
  • Silicon-on-insulator substrate and method of forming
    Patent number: 8536035
    Abstract: Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (Oi) concentration of less than approximately 10 parts per million atoms (ppma). The method further includes counter-doping a surface region of the handle, causing the surface region to have a resistivity greater than approximately 3 kOhm-cm, and joining the surface region of the handle substrate with a donor wafer.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, Kenneth F. McAvey, Gerd Pfeiffer, Richard A. Phelps
  • SWITCHABLE FILTERS AND DESIGN STRUCTURES
    Publication number: 20130214877
    Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James W. ADKISSON, Panglijen CANDRA, Thomas J. DUNBAR, Mark D. JAFFE, Anthony K. STAMPER, Randy L. WOLF
  • Isolation structures for global shutter imager pixel, methods of manufacture and design structures
    Patent number: 8507962
    Abstract: Pixel sensor cells, e.g., CMOS optical imagers, methods of manufacturing and design structures are provided with isolation structures that prevent carrier drift to diffusion regions. The pixel sensor cell includes a photosensitive region and a gate adjacent to the photosensitive region. The pixel sensor cell further includes a diffusion region adjacent to the gate. The pixel sensor cell further includes an isolation region located below a channel region of the gate and about the photosensitive region, which prevents electrons collected in the photosensitive region to drift to the diffusion region.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Mark D. Jaffe
  • SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING
    Publication number: 20130196493
    Abstract: Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (Oi) concentration of less than approximately 10 parts per million atoms (ppma). The method further includes counter-doping a surface region of the handle, causing the surface region to have a resistivity greater than approximately 3 kOhm-cm, and joining the surface region of the handle substrate with a donor wafer.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, Kenneth F. McAvey, Gerd Pfeiffer, Richard A. Phelps
  • BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE
    Publication number: 20130187246
    Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 25, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James W. ADKISSON, Panglijen CANDRA, Thomas J. DUNBAR, Jeffrey P. GAMBINO, Mark D. JAFFE, Anthony K. STAMPER, Randy L. WOLF
  • SWITCHABLE FILTERS AND DESIGN STRUCTURES
    Publication number: 20130187729
    Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a fixed electrode with a plurality of fingers on the piezoelectric substrate. The method further includes forming a moveable electrode with a plurality of fingers over the piezoelectric substrate. The method further includes forming actuators aligned with one or more of the plurality of fingers of the moveable electrode.
    Type: Application
    Filed: January 25, 2012
    Publication date: July 25, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James W. ADKISSON, Panglijen CANDRA, Thomas J. DUNBAR, Jeffrey P. GAMBINO, Mark D. JAFFE, Anthony K. STAMPER, Randy L. WOLF
  • Passivated through wafer vias in low-doped semiconductor substrates
    Patent number: 8492272
    Abstract: A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Alvin J. Joseph