Patents by Inventor Mark Hiatt
Mark Hiatt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11887969Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.Type: GrantFiled: February 28, 2022Date of Patent: January 30, 2024Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck
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Publication number: 20220415855Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.Type: ApplicationFiled: February 28, 2022Publication date: December 29, 2022Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck
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Patent number: 11264360Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.Type: GrantFiled: October 28, 2019Date of Patent: March 1, 2022Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck
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Publication number: 20200058621Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.Type: ApplicationFiled: October 28, 2019Publication date: February 20, 2020Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck
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Patent number: 10468382Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.Type: GrantFiled: April 25, 2016Date of Patent: November 5, 2019Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck
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Patent number: 10446440Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: GrantFiled: August 21, 2018Date of Patent: October 15, 2019Assignee: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Publication number: 20180358263Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: ApplicationFiled: August 21, 2018Publication date: December 13, 2018Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Patent number: 10062608Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: GrantFiled: May 2, 2017Date of Patent: August 28, 2018Assignee: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Publication number: 20170283954Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: ApplicationFiled: May 2, 2017Publication date: October 5, 2017Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Patent number: 9678019Abstract: A lumber check grader-actuatable interface enables a check grader to interact with grade-quality measured boards of lumber conveyed along a flow path and passing in front of the check grader. The interface accurately and continuously tracks the location of each board in front of a check grader and tracks the location of the check grader's hands relative to the boards. Gestures can, therefore, be used for a selected board to perform additional actions, such as changing the grade or changing the trims. The interface enables a check grader to walk alongside and keep pace with a board of interest as it is transported and to provide feedback to the interface about a needed change for the board of interest. By knowing which board is of interest to a check grader, the interface can display additional information for only that board without overwhelming the check grader with non-stop information overload.Type: GrantFiled: September 15, 2015Date of Patent: June 13, 2017Assignee: Lucidyne Technologies, Inc.Inventors: Aaron R. Paul, Josh Miller, Mark Miller, Wendy Roberts, Mark Hiatt, Hayden Michael Aronson
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Patent number: 9640433Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: GrantFiled: February 10, 2014Date of Patent: May 2, 2017Assignee: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Publication number: 20170074805Abstract: A lumber check grader-actuatable interface enables a check grader to interact with grade-quality measured boards of lumber conveyed along a flow path and passing in front of the check grader. The interface accurately and continuously tracks the location of each board in front of a check grader and tracks the location of the check grader's hands relative to the boards. Gestures can, therefore, be used for a selected board to perform additional actions, such as changing the grade or changing the trims. The interface enables a check grader to walk alongside and keep pace with a board of interest as it is transported and to provide feedback to the interface about a needed change for the board of interest. By knowing which board is of interest to a check grader, the interface can display additional information for only that board without overwhelming the check grader with non-stop information overload.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Inventors: Aaron R. Paul, Josh Miller, Mark Miller, Wendy Roberts, Mark Hiatt, Hayden Michael Aronson
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Publication number: 20160240515Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.Type: ApplicationFiled: April 25, 2016Publication date: August 18, 2016Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck
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Patent number: 9324690Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.Type: GrantFiled: January 30, 2012Date of Patent: April 26, 2016Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck
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Publication number: 20140154879Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: ApplicationFiled: February 10, 2014Publication date: June 5, 2014Applicant: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Patent number: 8687294Abstract: An optics block includes a substrate having first and second opposing surfaces, the substrate being a first material, a plurality of through holes extending in the substrate between the first and second opposing surface, a second material, different than the first material, filling a portion of the through holes and extending on a portion of the first surface of the substrate outside the through holes, and a first lens structure in the second material and corresponding to each of the through holes.Type: GrantFiled: May 25, 2012Date of Patent: April 1, 2014Assignee: Digitaloptics CorporationInventors: Gregory J. Kintz, Michael R. Feldman, James E. Morris, Paul Elliott, David Keller, W. Hudson Welch, David Ovrutsky, Jeremy Huddleston, Mark Hiatt
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Patent number: 8531046Abstract: The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined.Type: GrantFiled: May 3, 2011Date of Patent: September 10, 2013Assignee: Micron Technology, Inc.Inventors: Dave Pratt, Kyle K. Kirby, Steve Oliver, Mark Hiatt
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Publication number: 20130036606Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.Type: ApplicationFiled: January 30, 2012Publication date: February 14, 2013Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck
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Patent number: 8324100Abstract: Methods of forming a conductive via may include forming a blind via hole partially through a substrate, forming an aluminum film on surfaces of the substrate, removing a first portion of the aluminum film from some surfaces, selectively depositing conductive material onto a second portion of the aluminum film, and exposing the blind via hole through a back side of the substrate. Methods of fabricating a conductive via may include forming at least one via hole through at least one unplated bond pad, forming a first adhesive over at least one surface of the at least one via hole, forming a dielectric over the first adhesive, forming a base layer over the dielectric and the at least one unplated bond pad, and plating nickel onto the base layer.Type: GrantFiled: February 17, 2011Date of Patent: December 4, 2012Assignee: Micron Technology, Inc.Inventors: Salman Akram, William Mark Hiatt, Steven Oliver, Alan G. Wood, Sidney B. Rigg, James M. Wark, Kyle K. Kirby
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Patent number: 8294273Abstract: Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.Type: GrantFiled: January 6, 2011Date of Patent: October 23, 2012Assignee: Micron Technology, Inc.Inventors: Salman Akram, William Mark Hiatt, Steve Oliver, Alan G. Wood, Sidney B. Rigg, James M. Wark, Kyle K. Kirby