Abstract: An apparatus includes a first scanning laser configured to generate a first process beam, a second scanning laser configured to generate a second process beam, one or more beam splitters, a beam modulator, an optical bench and a beam steering module. The optical bench has a first optical hole configured to receive the first process beam via the one or more beam splitters and the beam modulator, and a second optical hole configured to receive the second process beam via the one or more beam splitters and the beam modulator. The beam steering module is configured to laterally scan the first process beam, the second process beam or both.

Abstract: A method of wafer processing includes generating a first process beam by a first scanning laser, generating a second process beam by a second scanning laser, directing the first process beam through a first optical hole of an optical bench to a surface of a first wafer placed on a first wafer holder, directing the second process beam through a second optical hole of the optical bench, and laterally scanning the first process beam, the second process beam or both.

Abstract: A method of wafer handling includes providing a wafer on a wafer carrier on a wafer chuck on a vacuum plate. The wafer carrier includes a permanent magnet. The wafer chuck includes an electromagnet. The wafer is raised against a gravity direction by flowing an electrical current through the electromagnet so that the wafer carrier is repelled from the wafer chuck while the wafer remains on the wafer carrier. While keeping the wafer raised, wafer alignment is adjusted by moving the wafer chuck, the wafer carrier or both. The electrical current is reduced to zero so that the wafer carrier contacts the wafer chuck. The wafer is connected to the vacuum plate via a first vacuum cavity of the wafer chuck and a third vacuum cavity of the wafer carrier. The wafer carrier is connected to the vacuum plate via the second vacuum cavity of the wafer chuck.

Abstract: A semiconductor device includes a substrate with a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure which is vertically arranged with respect to the working surface. The complex channel structure includes first and second source-drain (S-D) ends which are provided in a plane extending along the working surface to define an opening to a bounded region of the complex channel structure. The transistor also includes a gate dielectric layer formed on the complex channel structure within the bounded region, and a gate metal layer formed on the gate dielectric layer within the bounded region to form the transistor.

Abstract: A semiconductor device includes a stack of layers, a vertical channel structure and vertical contact structures. The stack of layers defines a sidewall surface and includes terminal layers which include source, gate and drain layers. The vertical channel structure defines an inner axis that is substantially transverse to a main surface of the stack of layers. The vertical contact structures are each configured to electrically connect to a respective terminal layer. At least two vertical contact structures are in different radial positions relative to the inner axis.

Abstract: Techniques herein provide thermal processing solutions applicable to both existing FINFET applications, including wrap-around contacts, as well as 3D architectures such as transistor-on-transistor and gate-on-gate monolithic or heterogeneous CFET. Techniques include heating or annealing a first target material without heating or affecting performance of a second material or other materials. Techniques include using a first heating process to heat a substrate and materials provided thereon to a first temperature, and then using a wavelength/frequency tunable second heating process to increase temperature of the target material without increasing temperature of the second material or other materials.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The semiconductor device includes a first metal structure extending in a first lateral direction. The semiconductor device includes a first ferroelectric layer surrounding a first portion of the first metal structure. The semiconductor device includes a first channel layer surrounding the first ferroelectric layer. The semiconductor device includes a first gate structure surrounding the first portion of the first metal structure, with the first ferroelectric layer and the first channel layer interposed therebetween. The semiconductor device includes a first gate electrode in electrical contact with the first gate structure. The semiconductor device includes a second gate electrode in electrical contact with a second portion of the first metal structure.

Abstract: Aspects of the disclosure provide a hybrid bonding method that includes measuring an electrical characteristic distribution for each of a first wafer and multiple second wafers, the electrical characteristic distribution of each wafer indicating at least one of a distribution of saturation current values of dies of the respective wafer, a distribution of cut-off current values of the dies of the respective wafer, and a distribution of ring oscillator data of the dies of the respective wafer; based on the electrical characteristic distributions of the first wafer and the multiple second wafers, executing a die pairing process that selects a plurality of dies from the multiple second wafers and pairs the selected plurality of dies with the dies of the first wafer to form a plurality of groups of dies; and performing a pick-and-place die-to-chip bonding process to bond the plurality of groups of dies.

Abstract: A wafer measurement stage for supporting a semiconductor wafer for surface geometry measurements. The wafer measurement stage includes a support body having a planar surface configured to face a wafer which is supported by the wafer measurement stage, and a wafer contact structure provided on the planar surface. The wafer contact structure is configured to contact a portion of a wafer such that the wafer is supported in an elevated position relative to the planar surface and to control gravity effects at non-contact portions of the wafer.

Abstract: Aspects of the disclosure provide a hybrid bonding method that includes measuring an overlay registration distribution and a metal recess depth distribution for each of a first wafer and multiple second wafers, the overlay registration distribution of each wafer indicating a distribution of overlay registration values of dies of the respective wafer, and the metal recess depth distribution of each wafer indicating a distribution of metal recess depths of bonding regions of the dies of the respective wafer; based on the overlay registration distributions and the metal recess depth distributions of the first wafer and the multiple second wafers, executing a die pairing process that selects a plurality of dies from the multiple second wafers and pairs the selected plurality of dies with the dies of the first wafer to form a plurality of pairs of dies; and executing an anneal process to bond the plurality of pairs of dies.

Abstract: A method of fabricating a semiconductor device includes forming on a patterned multilayered stack including sacrificial layers alternatingly stacked with channel layers on a substrate, the patterned multilayered stack having opposing sidewalls and opposing ends. Cantilever supports are formed on the substrate, each cantilever support being in contact with a respective opposing end of the patterned multilayered stack. A gate-all-around (GAA) structure is formed around each channel layer while the opposing ends of the multilayered stack are supported by the cantilever supports. The cantilever supports are removed from the opposing ends of the patterned multilayered stack to expose end portions of each channel layer, and source-drain (S-D) regions are formed on the exposed end portions of each respective channel layer.

Abstract: Aspects of the present disclosure provide a system for localized wafer pre-cooling for a hyperspectral imaging system. For example, the system can include a wafer chuck configured for holding a wafer thereon and moving and locating the wafer at a variety of heights. The system can further include a cooling fluid injection device configured for injecting a cooling fluid on a surface of the wafer held on the wafer chuck. The system can further include an optical column configured for directing a light beam through the cooling fluid onto the surface of the wafer. The system can further include an imaging device configured for capturing images of the wafer located at different heights and generating a three-dimension (3D) image based on the captured images.

Abstract: A device includes a first die including first integrated circuitry and first conductive wiring layers. The first conductive wiring layers include a power line and a ground line. The device also includes a second die including second integrated circuitry and second conductive wiring layers. The second conductive wiring layers include no power line and no ground line. The first die is aligned with and bonded to the second die. The first conductive wiring layers are electrically connected with the second conductive wiring layers. The second die uses the power line and the ground line of the first die.

Abstract: A semiconductor device includes a substrate having a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure including a main portion extending in a main direction along the working surface, and tail portions each connected to a respective end of the main portion and extending along the working surface in a different direction from the main direction, a distal end of each tail portion including a source-drain (S-D) end such that the S-D ends are offset from the main portion of the complex channel structure. A gate all around (GAA) structure formed around only the main portion of the complex channel structure between the tail portions, and S-D contacts formed on respective S-D ends of the complex channel structure such that the S-D contacts are offset from the GAA structure.

Abstract: Systems and methods are provided herein for determining the planarity of a semiconductor substrate. The systems and methods described herein use a metrology tool that utilizes a non-contact, laser-scanning technique to determine the planarity a semiconductor substrate. The metrology tool disclosed herein uses a fixed optical system to measure the slope of the substrate surface at multiple points across the substrate surface as the semiconductor substrate is moved in at least one direction (e.g., an x and/or y direction). The slope measurements obtained across the substrate surface are then combined to determine a surface profile of the semiconductor substrate, or used to calculate the amount of bow or warp attributed to the substrate surface.

Abstract: Techniques herein provide thermal processing solutions applicable to both existing FINFET applications, including wrap-around contacts, as well as 3D architectures such as transistor-on-transistor and gate-on-gate monolithic or heterogeneous CFET. Techniques include heating or annealing a first target material without heating or affecting performance of a second material or other materials. Techniques include using a first heating process to heat a substrate and materials provided thereon to a first temperature, and then using a wavelength/frequency tunable second heating process to increase temperature of the target material without increasing temperature of the second material or other materials.

Abstract: A method of 3D imaging includes immersing an objective lens of a microscope at least partially in a liquid film formed on a wafer. The objective lens is spaced apart from the wafer. The microscope includes a light source configured to emit light of one or more wavelengths. A first image of a region within the wafer is captured using the one or more wavelengths. The wafer is reoriented relative to the region. The reorienting includes at least one of tilting the wafer or rotating the wafer. The reorienting is performed while keeping the objective lens at least partially immersed in the liquid film and spaced apart from the wafer. A second image of the region is captured using the one or more wavelengths.

Abstract: A method of 3D imaging includes immersing an objective lens of a microscope at least partially in a liquid film formed on a wafer. The objective lens is spaced apart from the wafer. The microscope includes a light source configured to emit light of one or more wavelengths. A first image of a region within the wafer is captured using the one or more wavelengths. The wafer is moved toward or away from the objective lens while the objective lens is kept at least partially immersed in the liquid film and spaced apart from the wafer. A second image of the region is captured using the one or more wavelengths.

Abstract: Aspects of the present disclosure provide an apparatus. For example, the apparatus can include a wafer holder for holding a wafer, a light reflection device located beside a wafer edge and having a light reflection surface tilted with respect to a wafer surface, and a coherent light source for generating incident light to perform a scan on the wafer surface and the light reflection surface, which can reflect the incident light to generate reflection light, which can be detected by a light detector. The coherent light source, the light reflection device and the light detector can be arranged such that the incident light passes by the wafer edge and the reflection light generated by the light reflection surface is detected by the light detector or the reflection light generated by the light reflection surface passes by the wafer edge and is detected by the light detector.

Abstract: An apparatus for measuring bow of a wafer, includes a substrate holder having a support surface configured to support a wafer; and a capacitor array unit including a plurality of electrodes laterally spaced from one another in the capacitor array unit. Each electrode faces the support surface and is spaced a respective fixed distance from the support surface such that each electrode can form a capacitor with an opposing area of a substrate provided on the support surface of the substrate holder.