Abstract: A method of fabricating a semiconductor device includes forming on a patterned multilayered stack including sacrificial layers alternatingly stacked with channel layers on a substrate, the patterned multilayered stack having opposing sidewalls and opposing ends. Cantilever supports are formed on the substrate, each cantilever support being in contact with a respective opposing end of the patterned multilayered stack. A gate-all-around (GAA) structure is formed around each channel layer while the opposing ends of the multilayered stack are supported by the cantilever supports. The cantilever supports are removed from the opposing ends of the patterned multilayered stack to expose end portions of each channel layer, and source-drain (S-D) regions are formed on the exposed end portions of each respective channel layer.

Abstract: A microfabricated transistor device includes a vertical stack of two or more channels of field effect transistors on a semiconductor substrate. Each of the channels has a vertical conductive path relative to a surface of the semiconductor substrate. At least one of the channels includes a shell formed around a core material, the shell including epitaxial material. The vertical stack can include a channel for a PMOS field effect transistor, and a channel for an NMOS field effect transistor.

Abstract: A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

Abstract: A method of fabricating a semiconductor device includes forming a patterned stack of layers including at least one lower active layer for forming a lower transistor and at least one upper active layer for forming an upper transistor stacked on the lower transistor. A dummy gate is formed surrounding a gate portion of each of the lower active layers and each of the upper active layers in the patterned stack, and the source-drain portions of the lower active layers and the upper active layers are doped. Source-drain connections to doped source-drain portions of the lower active layers and the upper active layers are formed. The dummy gate of the lower active layers and the upper active layers is replaced with a gate-all-around (GAA) structure to form the lower transistor and the upper transistor.

Abstract: Methods for the manufacture of three-dimensional (3D) semiconductor devices are disclosed. Aspects can include forming a patterned first conductive source/drain structure of a transistor structure, forming a gate patterned conductive structure of the transistor structure separated from the first conductive source/drain structure by at least one dielectric layer, forming a patterned second conductive source/drain structure of the transistor structure separated from the gate patterned conductive structure by at least one dielectric layer, forming a transistor body opening extending through the transistor structure, forming a gate dielectric in the transistor body opening, and forming a material in the transistor body opening extending from the patterned first conductive source/drain structure to the patterned second conductive source/drain structure.

Abstract: A semiconductor device includes a substrate having a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure including a main portion extending in a main direction along the working surface, and tail portions each connected to a respective end of the main portion and extending along the working surface in a different direction from the main direction, a distal end of each tail portion including a source-drain (S-D) end such that the S-D ends are offset from the main portion of the complex channel structure. A gate all around (GAA) structure formed around only the main portion of the complex channel structure between the tail portions, and S-D contacts formed on respective S-D ends of the complex channel structure such that the S-D contacts are offset from the GAA structure.

Abstract: In some implementations, the device may include a vertical transistor having a first source/drain (s/d) region adjacent a substrate, a channel region above the first s/d region, and a second s/d region. In addition, the device includes a capacitor having two conductive regions separated by a dielectric region, one of the two conductive regions electrically coupled to the second s/d region.

Abstract: A method of microfabrication is provided. The method includes forming shell structures above a first layer including a first semiconductor material. The shell structures are electrically isolated from each other and electrically isolated from the first layer. The shell structures include at least one type of semiconductor material and each include a dielectric core structure. Each shell structure is configured to include a top source/drain (S/D) region, a channel region and a bottom S/D region serially connected in a vertical direction perpendicular to the first layer and have a current flow path in the vertical direction. A bottom contact structure connected to a respective bottom S/D region of each shell structure is formed. A gate structure is formed on a sidewall of a respective channel region of each shell structure.

Abstract: A memory element and method of formation is disclosed that includes a transistor integrated with a capacitor through a common nanosheet. The transistor includes a channel, a source region, a drain region and a gate component on at least one side of the channel between the source region and drain region. The channel is formed in a first portion of a nanosheet. The capacitor has a first capacitor component and second capacitor component separated by an insulator. The first capacitor component is provided in a second portion of the nanosheet.

Abstract: Aspects of the present disclosure provide a bonding device for bonding two wafers. For example, the bonding device can include a first bonding chuck and a second bonding chuck. The first bonding chuck can have a first bonding head for a first wafer to be mounted thereon. The second bonding chuck can have a plurality of second bonding heads for a second wafer to be mounted thereon. The second bonding heads can be controlled individually to apply local pressures onto the second wafer to move the second wafer toward the first wafer to bond the second wafer to the first wafer, the local pressures corresponding to bow measurement of the first wafer and the second wafer.

Abstract: Apparatuses, devices and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

Abstract: Aspects of the present disclosure provide a method for improving overlay alignment of patterning by correcting wafer shape. For example, the method can include receiving a wafer having a working surface with at least partially-fabricated semiconductor devices, and a backside surface opposite to the working surface. The method can also include forming a first stressor film on the backside surface. The first stressor film can modify overlay alignment of the working surface in a first direction across the working surface of the wafer. The method can also include forming one or more first semiconductor structures on the working surface of the wafer. The first semiconductor structures are aligned in the first direction.

Abstract: Aspects of the present disclosure provide a method of fabricating a semiconductor device including a plurality of vertically stacked transistors. For example, the method can include providing a vertical stack of alternating horizontal first and second layers, the second layers forming channels of the transistors. The method can further include uncovering the second layers. The method can further include forming a first shell on a first one of the uncovered second layers, the first shell and the first one of the uncovered second layers forming a first channel structure of a first one of the transistors.

Abstract: A semiconductor device includes a substrate having a substrate surface, a transistor stack provided on the substrate surface and including a plurality of transistors stacked on each other along a vertical direction that is perpendicular to the substrate surface. Each transistor in the transistor stack includes a vertical channel structure extending along the vertical direction and having a first vertical sidewall and a second vertical sidewall opposite to the first vertical sidewall, and a ferroelectric gate structure in contact with the first vertical sidewall of the vertical channel structure; and a back gate structure provided on the substrate and in contact with the second vertical sidewall of the vertical channel structure of each respective transistor in the transistor stack.

Abstract: A semiconductor structure includes semiconductor layers stacked vertically over a substrate. The structure includes a gate structure interleaved with the semiconductor layers, where the gate structure wraps around a first end portion of each semiconductor layer. The structure includes dielectric layers stacked vertically over the substrate and interleaved with the semiconductor layers, where a first end portion of each dielectric layer is aligned with a second end portion of each semiconductor layer, which is laterally opposite to the first end portion of each semiconductor layer. The structure includes a metal contact extending vertically to contact the second end portion of each semiconductor layer.

Abstract: A method includes forming a fin structure over a substrate, the fin structure including alternating first semiconductor layers and second semiconductor layers stacked along a vertical direction; forming a dummy gate structure over the fin structure; selectively depositing an outer spacer layer on the dummy gate structure; performing a plasma doping process to form source/drain regions in each second semiconductor layer adjacent the dummy gate structure, where a portion of each second semiconductor layer interposing between the source/drain regions defines a channel region; forming a dielectric layer over the fin structure; removing the dummy gate structure to form a gate trench in the dielectric layer; selectively removing the first semiconductor layers to form openings interleaved with the second semiconductor layers; and forming a metal gate structure to fill the gate trench and the openings.

Abstract: A method includes forming a fin structure over a substrate, the fin structure including alternating first semiconductor layers and second semiconductor layers stacked along a vertical direction; forming a dummy gate structure over the fin structure; performing a plasma doping process to form source/drain regions in each second semiconductor layer adjacent the dummy gate structure, where a portion of each second semiconductor layer interposing between the source/drain regions defines a channel region; forming a dielectric layer over the fin structure; removing the dummy gate structure to form a gate trench in the dielectric layer; selectively removing the first semiconductor layers to form openings interleaved with the second semiconductor layers; depositing an inner spacer layer to partially fill the gate trench and the openings, wherein the inner spacer layer overlaps with the source/drain regions along the lateral direction; and forming a metal gate structure over the inner spacer layer.

Abstract: A method for fabricating and a structure comprising one or more transistors where a transistor includes one or more nanosheets formed based on one or more layers of a nanosheet material. A layer of shell material can at least partly surround the one or more nanosheets to form one or more channels of the transistor. A gate structure of the transistor can at least partly surround each of the one or more channels. The gate structure can include a gate dielectric disposed between the layer of the shell material and a gate metal of the gate structure for each of the nanosheets, where the shell material can include a charge carrier mobility that is greater than a charge carrier mobility of the nanosheet material.

Abstract: A transistor structure may include a first transistor beside a second transistor. The first transistor can include a first nanosheet oriented horizontally and forming a first channel, a second nanosheet oriented horizontally and forming a second channel, and a first gate structure disposed between and at least partly surrounding the first channel and the second channel. The second transistor can include a third nanosheet oriented horizontally and forming a third channel, a fourth nanosheet oriented horizontally and forming a fourth channel, and a second gate structure disposed between and at least partly surrounding the third channel and the fourth channel. The first nanosheet can be disposed above the third nanosheet, the third nanosheet is disposed above the second nanosheet, and the second nanosheet is disposed above the fourth nanosheet.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming a first stack over a substrate including first dielectric layers and second dielectric layers alternately stacked on top of one another. The method includes replacing first, second, and third portions of the first stack with first, second, and third dielectric structures, respectively. The method includes replacing the first dielectric structure with a second stack including first semiconductor layers and second semiconductor layers alternately stacked on top of one another. The method includes removing a portion of the second dielectric structure and a portion of the third dielectric structure. The method includes exposing sidewalls of each of the second semiconductor layers. The method includes forming a pair of first epitaxial structures and a pair of second epitaxial structures in contact with the exposed sidewalls of a lower one and an upper one of the second semiconductor layers, respectively.