Abstract: Aspects of the present disclosure provide a method for fabricating a semiconductor structure. For example, the method can include forming a stack of metal structures on a substrate, the stack of metal structures including multiple metal structures that are vertically stacked over and electrically separated from one another, each of the metal structures including a ring and one or more pad contacts extending from the ring, the rings of the metal structures being vertically aligned with one another. The method can also include forming one or more channel structures within the rings of the metal structures, the channel structures being electrically separated from one another and electrically separated from the substrate. The method can also include forming one or more interconnections that extend from a position above the stack of metal structures to corresponding one or more of the pad contacts of the metal structures.

Abstract: Three-dimensional (3D) NAND memory structures and methods to manufacture 3D NAND memory structures are disclosed. A method includes forming a stack of layers that includes a first sub-stack for a transistor structure and a second sub-stack for a memory structure positioned on the first sub-stack. The second sub-stack includes at least one layer of conductive material and at least one layer of non-conductive material. The first sub-stack and the second sub-stack are separated by at least one non-conductive layer. The method includes forming a channel opening in the stack of layers, forming a gate dielectric in the channel opening, and providing a channel structure within the channel opening. The channel structure includes a semiconductive-behaving material and aligned with the transistor structure. The method includes providing a charge trap layer within the channel opening and aligned with the memory structure.

Abstract: FeFET memory devices are provided. A semiconductor device includes a first metal structure of a first gate electrode. The semiconductor device includes a gate dielectric structure extending along a bottom surface of the first metal structure and surrounding a sidewall of the first metal structure. The semiconductor device includes a semiconductor-behaving structure extending along a bottom surface of the gate dielectric structure and surrounding a sidewall of the gate dielectric structure. The semiconductor device includes a ferroelectric structure surrounding a sidewall of the semiconductor-behaving structure. The semiconductor device includes a second gate electrode comprising a second metal structure in contact with the semiconductor-behaving structure.

Abstract: A semiconductor device includes a first gate structure, a second gate structure, and a semiconductor layer. The first gate structure, the semiconductor layer, and the second gate structure are arranged concentrically. The first gate structure includes a first gate electrode and a ferroelectric layer. The second gate structure includes a second gate electrode and a gate dielectric layer. The semiconductor layer is disposed between the ferroelectric layer and the gate dielectric layer.

Abstract: An apparatus for measuring bow of a wafer, includes a substrate holder having a support surface configured to support a wafer; and a capacitor array unit including a plurality of electrodes laterally spaced from one another in the capacitor array unit. Each electrode faces the support surface and is spaced a respective fixed distance from the support surface such that each electrode can form a capacitor with an opposing area of a substrate provided on the support surface of the substrate holder.

Abstract: Structures and methods are disclosed in which a layer stack can be formed with a plurality of layers of a metal, where each of the layers of metal can be separated by a layer of a dielectric. An opening in the layer stack can be formed such that a semiconductor layer beneath the plurality of layers of the metal is uncovered. One or more vertical channel structures can be formed within the opening by epitaxial growth. The vertical channel structure can include a vertically oriented transistor. The vertical channel structure can include an interface of a silicide metal with a first metal layer of the plurality of metal layers. The interface can correspond to one of a source or a drain connection of a transistor. The silicide metal can be annealed above a temperature threshold to form a silicide interface between the vertical channel structure and the first metal layer.

Abstract: A semiconductor device includes a transistor structure that includes a two-dimensional (2D) material around at least a dielectric structure. The transistor structure includes a first source/drain structure in contact with the first 2D material. The transistor structure includes a second source/drain structure in contact with the 2D material. The transistor structure includes a gate structure around at least the 2D material.

Abstract: Methods for the manufacture of semiconductor devices with integrated two-dimensional (2D) materials are disclosed. Aspects can include forming a base structure comprising a seed material with a chemical element; forming source/drain contacts coupled to first and second portions of the base structure, respectively, wherein the source/drain contacts each have at least the chemical element; exposing a third portion of the base structure; selectively growing a 2D material at least coupled to the third portion of the base structure; and forming an active gate coupled to the 2D material.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming vertical channel structures on a substrate. The vertical channel structures are formed within a layer stack of alternating layers of a first metal and a first dielectric. The vertical channel structures are channels of field effect transistors that have a current flow path perpendicular to a surface of the substrate. The vertical channel structures have a dielectric core. The method includes forming openings on the substrate that uncover a region of the layer stack adjacent to the vertical channel structures. The method includes, for each vertical channel structure, forming a corresponding staircase region in the layer stack, and forming metal contacts within each staircase region.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The semiconductor device includes a first metal structure extending in a first lateral direction. The semiconductor device includes a first ferroelectric layer surrounding a first portion of the first metal structure. The semiconductor device includes a first channel layer surrounding the first ferroelectric layer. The semiconductor device includes a first gate structure surrounding the first portion of the first metal structure, with the first ferroelectric layer and the first channel layer interposed therebetween. The semiconductor device includes a first gate electrode in electrical contact with the first gate structure. The semiconductor device includes a second gate electrode in electrical contact with a second portion of the first metal structure.

Abstract: A semiconductor device may include a first dielectric layer, a first gate electrode, a first gate dielectric layer, a first source electrode, a first drain electrode, and a first two-dimensional (2D) semiconductor layer. The first dielectric layer may have a first top surface. The first gate electrode may extend from the first top surface into the first dielectric layer. The first gate dielectric layer may be disposed on the first gate electrode and have a second top surface. The first source electrode may extend from the second top surface, through the first gate dielectric layer and into the first dielectric layer. The first drain electrode may extend from the second top surface, through the first gate dielectric layer and into the first dielectric layer. The first 2D semiconductor layer may be disposed on the first gate dielectric layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and channel structures stacked over each other along a first direction substantially perpendicular to a working surface of the substrate and each configured to have a current direction along a second direction substantially parallel to the working surface of the substrate. Source/drain (S/D) structures are positioned on opposing sides of the channel structure along the second direction. Gate structures are positioned on opposite sides of the channel structures along a third direction substantially parallel to the working surface of the substrate. The channel structures each have a shape of a nanosheet extending substantially perpendicular to the working surface of the substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a pair of channel structures each configured to have a current direction along a first direction substantially parallel to a working surface of a substrate. The semiconductor device also includes source/drain (S/D) structures on opposing sides of the pair of channel structures along the first direction. The semiconductor device further includes a gate structure between the pair of channel structures. The pair of channel structures includes two-dimensional (2D) semiconductor material oriented substantially perpendicular to the working surface of the substrate.

Abstract: The disclosed technology generally relates to a process of forming transistors with high-k dielectric layers, such as selectively high-k dielectric layers. The high-k dielectric layers, which may be used as the gate dielectric, may be selectively grown from two-dimensional semiconductor materials. The process may be adapted for various transistor structures such as planar transistors, three-dimensional transistors, and gate-all-around transistors. Further, the process may also be used to create stacked transistors. In one aspect, a method for manufacturing a semiconductor device includes forming a seed structure over a base layer, forming a two-dimensional (2D) semiconductor layer disposed on the seed structure, and selectively growing a high-k dielectric layer over the 2D semiconductor layer.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The semiconductor device includes a first semiconductor structure extending along a vertical direction; a high-k dielectric layer disposed around at least the first semiconductor structure; a first metal structure disposed around the first semiconductor structure, with the high-k dielectric layer interposed therebetween; a ferroelectric structure disposed around the first semiconductor structure, with the high-k dielectric layer and the first metal structure interposed therebetween; and a second metal structure having a portion disposed around the first semiconductor structure, with the high-k dielectric layer, the first metal structure, and the ferroelectric structure interposed therebetween.

Abstract: Disclosed herein are related to a device including vertically placed semiconductor devices in a trench, and a method of fabricating the vertically placed semiconductor devices. In one aspect, a device includes a substrate including a trench defined by a first sidewall and a second sidewall facing each other along a first direction, and a floor between one end of the first sidewall and one end of the second sidewall. The device may include two or more vertical slots separated by vertical nano sheets extending upwards from the floor within the trench. In one aspect, the semiconductor devices can be formed in the two or more vertical slots. For example, source/drain structures, gate structures, and additional source/drain structures of vertical transistors can be formed in the two or more vertical slots.

Abstract: Vertical transistors and methods of manufacturing vertical transistors are disclosed. The method can include forming a stack of layers include a first layer stack of a first transistor structure including at least three layers of a conductive material separated by one or more layers of at least one dielectric material. The stack of layers can include a second layer stack of a second transistor structure including at least three layers of a conductive material separated by one or more layers of at least one dielectric material, the second layer stack associated with a second transistor structure. The first and second transistor structures are separated by one or more dielectric materials. The method can include forming a channel opening in the stack. The method includes selectively forming a first channel structure within the channel opening and selectively forming a second channel structure within the channel opening.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The devices may include a first epitaxial structure disposed below a dielectric pillar, a second epitaxial structure disposed above the first epitaxial structure and around the dielectric pillar, a third epitaxial structure disposed above the second epitaxial structure and around the dielectric pillar, and a fourth epitaxial structure disposed above the third epitaxial structure and around the dielectric pillar. The second and third epitaxial structures may each have a portion inwardly extending toward a central axis of the dielectric pillar.

Abstract: A semiconductor structure includes a stack of channel layers extending vertically over a substrate. The semiconductor structure includes a gate structure interleaved with the stack, where the gate structure wraps around a first end of each channel layer. The gate structure includes a dielectric layer over the channel layer, a ferroelectric layer over the dielectric layer, and a metal layer over the ferroelectric layer. The semiconductor structure includes an isolation structure disposed over a second end of each channel layer opposite the first end.

Abstract: A method of microfabrication includes epitaxially growing a first vertical channel structure of silicon-containing material on a first sacrificial layer of silicon containing material, the first sacrificial layer having etch selectivity with respect to the vertical channel structure. A core opening is directionally etched through the vertical channel structure to expose the first sacrificial layer, and the first sacrificial layer is isotropically etched through the core opening to form a first isolation opening for isolating the first vertical channel structure.