Abstract: A device includes a first die including first integrated circuitry and first conductive wiring layers. The first conductive wiring layers include a power line and a ground line. The device also includes a second die including second integrated circuitry and second conductive wiring layers. The second conductive wiring layers include no power line and no ground line. The first die is aligned with and bonded to the second die. The first conductive wiring layers are electrically connected with the second conductive wiring layers. The second die uses the power line and the ground line of the first die.

Abstract: A semiconductor device includes a substrate having a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure including a main portion extending in a main direction along the working surface, and tail portions each connected to a respective end of the main portion and extending along the working surface in a different direction from the main direction, a distal end of each tail portion including a source-drain (S-D) end such that the S-D ends are offset from the main portion of the complex channel structure. A gate all around (GAA) structure formed around only the main portion of the complex channel structure between the tail portions, and S-D contacts formed on respective S-D ends of the complex channel structure such that the S-D contacts are offset from the GAA structure.

Abstract: Systems and methods are provided herein for determining the planarity of a semiconductor substrate. The systems and methods described herein use a metrology tool that utilizes a non-contact, laser-scanning technique to determine the planarity a semiconductor substrate. The metrology tool disclosed herein uses a fixed optical system to measure the slope of the substrate surface at multiple points across the substrate surface as the semiconductor substrate is moved in at least one direction (e.g., an x and/or y direction). The slope measurements obtained across the substrate surface are then combined to determine a surface profile of the semiconductor substrate, or used to calculate the amount of bow or warp attributed to the substrate surface.

Abstract: Techniques herein provide thermal processing solutions applicable to both existing FINFET applications, including wrap-around contacts, as well as 3D architectures such as transistor-on-transistor and gate-on-gate monolithic or heterogeneous CFET. Techniques include heating or annealing a first target material without heating or affecting performance of a second material or other materials. Techniques include using a first heating process to heat a substrate and materials provided thereon to a first temperature, and then using a wavelength/frequency tunable second heating process to increase temperature of the target material without increasing temperature of the second material or other materials.

Abstract: A method of 3D imaging includes immersing an objective lens of a microscope at least partially in a liquid film formed on a wafer. The objective lens is spaced apart from the wafer. The microscope includes a light source configured to emit light of one or more wavelengths. A first image of a region within the wafer is captured using the one or more wavelengths. The wafer is reoriented relative to the region. The reorienting includes at least one of tilting the wafer or rotating the wafer. The reorienting is performed while keeping the objective lens at least partially immersed in the liquid film and spaced apart from the wafer. A second image of the region is captured using the one or more wavelengths.

Abstract: A method of 3D imaging includes immersing an objective lens of a microscope at least partially in a liquid film formed on a wafer. The objective lens is spaced apart from the wafer. The microscope includes a light source configured to emit light of one or more wavelengths. A first image of a region within the wafer is captured using the one or more wavelengths. The wafer is moved toward or away from the objective lens while the objective lens is kept at least partially immersed in the liquid film and spaced apart from the wafer. A second image of the region is captured using the one or more wavelengths.

Abstract: Aspects of the present disclosure provide an apparatus. For example, the apparatus can include a wafer holder for holding a wafer, a light reflection device located beside a wafer edge and having a light reflection surface tilted with respect to a wafer surface, and a coherent light source for generating incident light to perform a scan on the wafer surface and the light reflection surface, which can reflect the incident light to generate reflection light, which can be detected by a light detector. The coherent light source, the light reflection device and the light detector can be arranged such that the incident light passes by the wafer edge and the reflection light generated by the light reflection surface is detected by the light detector or the reflection light generated by the light reflection surface passes by the wafer edge and is detected by the light detector.

Abstract: An apparatus for measuring bow of a wafer, includes a substrate holder having a support surface configured to support a wafer; and a capacitor array unit including a plurality of electrodes laterally spaced from one another in the capacitor array unit. Each electrode faces the support surface and is spaced a respective fixed distance from the support surface such that each electrode can form a capacitor with an opposing area of a substrate provided on the support surface of the substrate holder.

Abstract: Techniques herein include methods of forming channel structures for field effect transistors having a channel current path parallel to a surface of a substrate. 3D in-situ horizontal or lateral growth of the channel and source/drain regions allows for a custom doping in the 3D horizontal nanosheet direction for NMOS and PMOS devices. An ultra-short channel length is achieved with techniques herein because the channel is epitaxially grown in the 3D horizontal nanosheet direction at the monolayer level. Since the channel is grown in a dielectric cavity, a precise channel cross sectional area can be tuned.

Abstract: A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. At least one DRAM cell unit includes a transistor and a capacitor. The capacitor includes a first metal layer, a capacitor dielectric layer positioned on the first metal layer, and a second metal layer positioned on the capacitor dielectric layer. The capacitor is elongated in a horizontal direction parallel to the working surface of the substrate. The second metal layer has a first end and a second end in the horizontal direction. The transistor includes a channel structure, and a gate structure disposed all around the channel structure. The first metal layer extends in the horizontal direction beyond the first end of the second metal layer to form a drain region and a source region of the transistor.

Abstract: A substrate processing apparatus includes a substrate holder configured to receive a substrate, a shaft connected to the substrate holder at one end of the shaft and configured to rotate the substrate holder, a plate attached to the shaft and configured to rotate with the shaft, magnets integrated with the substrate holder, the plate or both, and a coiled wire positioned between the substrate holder and the plate and configured to generate an electrical current when the shaft rotates. A method of energy generation includes providing the substrate processing apparatus and rotating the shaft to generate the electrical current.

Abstract: An apparatus for measuring bow of a wafer includes a substrate holder including a support surface configured to support a wafer, and an air flow system including a plurality of air outlets in the support surface which are configured to output air for elevating the wafer above the substrate holder. A capacitor array unit including a plurality of electrodes laterally spaced from one another in the capacitor array unit, each electrode facing the support surface and being spaced a respective fixed distance from the support surface such that each electrode can form a capacitor with an opposing area of a wafer elevated by the substrate holder.

Abstract: A method of wafer handling includes providing a wafer on a wafer carrier on a wafer chuck on a vacuum plate. The wafer carrier includes a permanent magnet. The wafer chuck includes an electromagnet. The wafer is raised against a gravity direction by flowing an electrical current through the electromagnet so that the wafer carrier is repelled from the wafer chuck while the wafer remains on the wafer carrier. While keeping the wafer raised, wafer alignment is adjusted by moving the wafer chuck, the wafer carrier or both. The electrical current is reduced to zero so that the wafer carrier contacts the wafer chuck. The wafer is connected to the vacuum plate via a first vacuum cavity of the wafer chuck and a third vacuum cavity of the wafer carrier. The wafer carrier is connected to the vacuum plate via the second vacuum cavity of the wafer chuck.

Abstract: A method of fabricating a semiconductor device includes receiving a first wafer including a first substrate on a backside of the first wafer, and a first semiconductor-on-insulator (SOI) stack on a front side of the first wafer. The first SOI stack includes a first semiconductor. A second wafer is received that includes a second substrate on a backside of the second wafer, and a second SOI stack on a front side of the second wafer. The second SOI stack includes a second semiconductor. The front side of the first wafer is bonded to the front side of the second wafer, via at least one dielectric bonding material, to form a bonded wafer. The second substrate is removed. A stack of transistor devices is formed with the first semiconductor used as a first channel for a first transistor and the second semiconductor used as a second channel for a second transistor.

Abstract: A method of microfabrication includes forming an initial stack of semiconductor layers by epitaxial growth over a substrate. The initial stack of semiconductor layers is surrounded by a sidewall structure. The initial stack of semiconductor layers includes channel structures and sacrificial gate layers stacked alternatingly in a vertical direction substantially perpendicular to a working surface of the substrate. The channel structures include a first channel structure and a second channel structure positioned above the first channel structure. First portions of the sidewall structure are removed to uncover first sides of the initial stack. Source/drain (S/D) regions are formed on uncovered side surfaces of the channel structures from the first sides of the initial stack. Second portions of the sidewall structure are removed to uncover second sides of the initial stack. The sacrificial gate layers are replaced with gate structures from the second sides of the initial stack.

Abstract: A system for testing metal recess depths into a wafer includes a test structure formed in the wafer, and probe pads positioned vertically over the test structure. The test structure includes a first region and a second region laterally adjacent to each other. The first region includes a dielectric layer having a top surface and a metal layer formed under the top surface. The second region includes the dielectric layer, the metal layer, and a first metal pad and a second metal pad laterally separated, vertically extend into the dielectric layer from the top surface, and in contact with the metal layer. The probe pads include a first and a second probe pads configured to be vertically over the first region, and a third and a fourth probe pads configured to be vertically over the second region and to align with the first and the second metal pads, respectively.

Abstract: A method of processing a substrate, including forming a photomask based on a layout of a first surface of a wafer including at least one opaque region and at least one transparent region and the first surface of the wafer being coated with a photosensitive resist; providing the photomask at a first photomask location between the first surface of the wafer and a source of radiation at a predetermined wavelength, the at least one opaque region of the photomask covering a first region of the first surface of the wafer and the at least one transparent region of the photomask exposing a second region of the first surface of the wafer; and exposing the first surface of wafer to a first pattern of radiation, the first pattern of radiation including the second region of the wafer exposed by the at least one transparent region of the photomask.

Abstract: Aspects of the present disclosure provide a semiconductor structure, which can include a lower transistor including a lower channel that is elongated horizontally and includes a lower doped first-type semiconductor layer of a lower doped semiconductor layer, an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally and includes an upper doped first-type semiconductor layer of an upper doped semiconductor layer, a lower capacitor electrically connected to and horizontally elongated from the lower transistor and including a first lower plate that includes a lower doped second-type semiconductor layer of the lower doped semiconductor layer, and an upper capacitor vertically stacked over the lower capacitor and electrically connected to and horizontally elongated from the upper transistor and including a first upper plate that includes an upper doped second-type semiconductor layer of the upper doped semiconductor layer.

Abstract: Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another can be provided. The plurality of first semiconductor channels each have a first sidewall in contact with a dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with the dielectric structure. Gate structures can be formed around at least a top surface, a bottom surface, and a second sidewall of the first and second semiconductor channels.

Abstract: A method of hybrid bonding includes accessing first dies sourced from a first wafer and second dies sourced from one or more second wafers. First overlay registration values (ORVs) of the first dies and second ORVs of the second dies are measured. A die pairing process is executed that matches the first dies with the second dies to form paired dies based on the first ORVs and the second ORVs. A hybrid bonding process is executed to bond the paired dies.