Abstract: Methods for the manufacture of semiconductor devices with integrated two-dimensional (2D) materials are disclosed. Aspects can include forming a base structure comprising a seed material with a chemical element; forming source/drain contacts coupled to first and second portions of the base structure, respectively, wherein the source/drain contacts each have at least the chemical element; exposing a third portion of the base structure; selectively growing a 2D material at least coupled to the third portion of the base structure; and forming an active gate coupled to the 2D material.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming vertical channel structures on a substrate. The vertical channel structures are formed within a layer stack of alternating layers of a first metal and a first dielectric. The vertical channel structures are channels of field effect transistors that have a current flow path perpendicular to a surface of the substrate. The vertical channel structures have a dielectric core. The method includes forming openings on the substrate that uncover a region of the layer stack adjacent to the vertical channel structures. The method includes, for each vertical channel structure, forming a corresponding staircase region in the layer stack, and forming metal contacts within each staircase region.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The semiconductor device includes a first metal structure extending in a first lateral direction. The semiconductor device includes a first ferroelectric layer surrounding a first portion of the first metal structure. The semiconductor device includes a first channel layer surrounding the first ferroelectric layer. The semiconductor device includes a first gate structure surrounding the first portion of the first metal structure, with the first ferroelectric layer and the first channel layer interposed therebetween. The semiconductor device includes a first gate electrode in electrical contact with the first gate structure. The semiconductor device includes a second gate electrode in electrical contact with a second portion of the first metal structure.

Abstract: A semiconductor device may include a first dielectric layer, a first gate electrode, a first gate dielectric layer, a first source electrode, a first drain electrode, and a first two-dimensional (2D) semiconductor layer. The first dielectric layer may have a first top surface. The first gate electrode may extend from the first top surface into the first dielectric layer. The first gate dielectric layer may be disposed on the first gate electrode and have a second top surface. The first source electrode may extend from the second top surface, through the first gate dielectric layer and into the first dielectric layer. The first drain electrode may extend from the second top surface, through the first gate dielectric layer and into the first dielectric layer. The first 2D semiconductor layer may be disposed on the first gate dielectric layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and channel structures stacked over each other along a first direction substantially perpendicular to a working surface of the substrate and each configured to have a current direction along a second direction substantially parallel to the working surface of the substrate. Source/drain (S/D) structures are positioned on opposing sides of the channel structure along the second direction. Gate structures are positioned on opposite sides of the channel structures along a third direction substantially parallel to the working surface of the substrate. The channel structures each have a shape of a nanosheet extending substantially perpendicular to the working surface of the substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a pair of channel structures each configured to have a current direction along a first direction substantially parallel to a working surface of a substrate. The semiconductor device also includes source/drain (S/D) structures on opposing sides of the pair of channel structures along the first direction. The semiconductor device further includes a gate structure between the pair of channel structures. The pair of channel structures includes two-dimensional (2D) semiconductor material oriented substantially perpendicular to the working surface of the substrate.

Abstract: The disclosed technology generally relates to a process of forming transistors with high-k dielectric layers, such as selectively high-k dielectric layers. The high-k dielectric layers, which may be used as the gate dielectric, may be selectively grown from two-dimensional semiconductor materials. The process may be adapted for various transistor structures such as planar transistors, three-dimensional transistors, and gate-all-around transistors. Further, the process may also be used to create stacked transistors. In one aspect, a method for manufacturing a semiconductor device includes forming a seed structure over a base layer, forming a two-dimensional (2D) semiconductor layer disposed on the seed structure, and selectively growing a high-k dielectric layer over the 2D semiconductor layer.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The semiconductor device includes a first semiconductor structure extending along a vertical direction; a high-k dielectric layer disposed around at least the first semiconductor structure; a first metal structure disposed around the first semiconductor structure, with the high-k dielectric layer interposed therebetween; a ferroelectric structure disposed around the first semiconductor structure, with the high-k dielectric layer and the first metal structure interposed therebetween; and a second metal structure having a portion disposed around the first semiconductor structure, with the high-k dielectric layer, the first metal structure, and the ferroelectric structure interposed therebetween.

Abstract: Vertical transistors and methods of manufacturing vertical transistors are disclosed. The method can include forming a stack of layers include a first layer stack of a first transistor structure including at least three layers of a conductive material separated by one or more layers of at least one dielectric material. The stack of layers can include a second layer stack of a second transistor structure including at least three layers of a conductive material separated by one or more layers of at least one dielectric material, the second layer stack associated with a second transistor structure. The first and second transistor structures are separated by one or more dielectric materials. The method can include forming a channel opening in the stack. The method includes selectively forming a first channel structure within the channel opening and selectively forming a second channel structure within the channel opening.

Abstract: Disclosed herein are related to a device including vertically placed semiconductor devices in a trench, and a method of fabricating the vertically placed semiconductor devices. In one aspect, a device includes a substrate including a trench defined by a first sidewall and a second sidewall facing each other along a first direction, and a floor between one end of the first sidewall and one end of the second sidewall. The device may include two or more vertical slots separated by vertical nano sheets extending upwards from the floor within the trench. In one aspect, the semiconductor devices can be formed in the two or more vertical slots. For example, source/drain structures, gate structures, and additional source/drain structures of vertical transistors can be formed in the two or more vertical slots.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The devices may include a first epitaxial structure disposed below a dielectric pillar, a second epitaxial structure disposed above the first epitaxial structure and around the dielectric pillar, a third epitaxial structure disposed above the second epitaxial structure and around the dielectric pillar, and a fourth epitaxial structure disposed above the third epitaxial structure and around the dielectric pillar. The second and third epitaxial structures may each have a portion inwardly extending toward a central axis of the dielectric pillar.

Abstract: A semiconductor structure includes a stack of channel layers extending vertically over a substrate. The semiconductor structure includes a gate structure interleaved with the stack, where the gate structure wraps around a first end of each channel layer. The gate structure includes a dielectric layer over the channel layer, a ferroelectric layer over the dielectric layer, and a metal layer over the ferroelectric layer. The semiconductor structure includes an isolation structure disposed over a second end of each channel layer opposite the first end.

Abstract: A method of microfabrication includes epitaxially growing a first vertical channel structure of silicon-containing material on a first sacrificial layer of silicon containing material, the first sacrificial layer having etch selectivity with respect to the vertical channel structure. A core opening is directionally etched through the vertical channel structure to expose the first sacrificial layer, and the first sacrificial layer is isotropically etched through the core opening to form a first isolation opening for isolating the first vertical channel structure.

Abstract: A method includes receiving a first device wafer comprising a plurality of dies, bonding a first side of a temporary wafer to a first side of the first device wafer to form a combined wafer, and performing a first patterning process on the combined wafer to form first trenches in the combined wafer. The first trenches fully extend through the first device wafer and partially into the temporary wafer from the first side of the temporary wafer. The first trenches separate the plurality of dies from each other. The method further includes placing the combined wafer on a support and applying a force to the combined wafer to separate the temporary wafer into individual temporary regions. Each individual temporary region is bonded to a respective individual die. The method further includes attaching individual dies to a second device wafer and removing the individual temporary regions from the individual dies.

Abstract: Structures and methods are disclosed in which a layer stack can be formed with a plurality of layers of a metal, where each of the layers of metal can be separated by a layer of a dielectric. An opening in the layer stack can be formed such that a semiconductor layer beneath the plurality of layers of the metal is uncovered. One or more vertical channel structures can be formed within the opening by epitaxial growth. The vertical channel structure can include a vertically oriented transistor. The vertical channel structure can include an interface of a silicide metal with a first metal layer of the plurality of metal layers. The interface can correspond to one of a source or a drain connection of a transistor. The silicide metal can be annealed above a temperature threshold to form a silicide interface between the vertical channel structure and the first metal layer.

Abstract: Methods for the manufacture of semiconductor devices constructed with two-dimensional (2D) materials and conductive oxides using three-dimensional (3D) nanosheets are disclosed. Aspects can include forming the stack of layers comprising a first layer of a semiconductive-behaving material separated from a base layer by a first layer of a first dielectric material and a first layer of a second dielectric material; a second layer of the semiconductive-behaving material separated from the first layer of the semiconductive-behaving material by a second layer of the second dielectric material; and a second layer of the second dielectric material formed on the second layer of the semiconductive-behaving material. Aspects include forming a metal contact coupled with the semiconductive-behaving material, forming a 2D material on the semiconductive-behaving material, forming a layer of a high-k dielectric material on the 2D material, and forming a gate metal on the high-k dielectric material.

Abstract: A semiconductor device includes a buried power rail (BPR) over a substrate and a semiconductor structure over the BPR. The semiconductor structure is tube-shaped and extends along a vertical direction. The semiconductor structure includes a first source/drain (S/D) region over the BPR, a gate region over the first S/D region, and a second S/D region over the gate region. The semiconductor device includes a first S/D interconnect structure extending from the BPR and further into the semiconductor structure such that a top portion of the first S/D interconnect structure is surrounded by the first S/D region. The semiconductor device includes a gate structure that includes (i) a gate oxide formed along an inner surface of the gate region and (ii) a gate electrode formed along sidewalls of the gate oxide in the gate region. The semiconductor device includes a second S/D interconnect structure positioned over the second S/D region.

Abstract: Example implementations can include a device with a core including a first dielectric material, the core having a mesa structure, a first layer disposed over opposite faces of the mesa structure of the core, the first layer including a metal material, and a second layer disposed over the mesa structure of the core and the first layer, the second layer including a two-dimensional material. Example implementations can include a method of manufacturing a stackable semiconductor device with a two-dimensional material layer, by depositing, over a substrate, a base layer including a first dielectric material, forming, on the base layer, at least one core having a mesa structure, forming sidewalls on opposite vertical surfaces of the mesa structure of the core, depositing, over the core and the sidewalls, a semiconductor layer including a two-dimensional material, and encapsulating the core, the sidewalls, and the semiconductor layer.

Abstract: A method of microfabrication includes epitaxially growing a first vertical channel structure of silicon-containing material on a first sacrificial layer of silicon containing material, the first sacrificial layer having etch selectivity with respect to the vertical channel structure. A core opening is directionally etched through the vertical channel structure to expose the first sacrificial layer, and the first sacrificial layer is isotropically etched through the core opening to form a first isolation opening for isolating the first vertical channel structure.

Abstract: Three-dimensional (3D) memory structures and methods to manufacture 3D memory structures are disclosed. A method includes forming a stack of layers including a first sub-stack for a first transistor structure, comprised of a first conductive layer, a gate layer, and a second source/drain layer. The stack of layers can include a second sub-stack for a memory structure positioned on the first sub-stack, the second sub-stack including at least one layer of conductive material and at least one layer of non-conductive material, and a third sub-stack for a second transistor structure. The method includes forming a channel opening in the stack of layers, providing a first channel structure within the channel opening, forming a memory dielectric layer in the channel opening and aligned with the memory structure, and providing a second channel structure in the channel opening in contact with the memory dielectric layer and aligned with the second transistor structure.