Abstract: A semiconductor device may include a transistor structure. The transistor structure may include a metal structure extending along a vertical direction; a gate dielectric layer around the metal structure; a channel layer around the gate dielectric layer; a first metal electrode disposed below the metal structure and in electrical contact with a first end of the channel layer; a second metal electrode disposed above the metal structure and in electrical contact with a second end of the channel layer; and a third metal electrode disposed above and in electrical contact with the metal structure.

Abstract: A semiconductor device may include a transistor structure. The transistor structure may include a metal structure extending along a vertical direction; a gate dielectric layer around the metal structure; a channel layer around the gate dielectric layer; a first metal electrode disposed below the metal structure and in electrical contact with a first end of the channel layer; a second metal electrode disposed above the metal structure and in electrical contact with a second end of the channel layer; and a third metal electrode disposed above and in electrical contact with the metal structure.

Abstract: A semiconductor device includes a first level having a plurality of transistor devices, and a first wiring level positioned over the first level. The first wiring level includes a plurality of conductive lines extending parallel to the first level, a plurality of conductive vertical interconnects extending perpendicular to the first level, and one or more programmable vertical interconnects that extend perpendicular to the first level and include a programmable material having a modifiable resistivity in that the one or more programmable vertical interconnects change between being conductive and being non-conductive according to a current pattern.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a first bottom contact positioned in a dielectric layer over a substrate, and a first channel structure extending from and in contact with the first bottom contact in a vertical direction perpendicular to the substrate. The first channel structure includes a bottom portion over the first bottom contact, a middle portion over the bottom portion, and a top portion over the middle portion. The semiconductor device includes a first gate structure positioned around the middle portion of the first channel structure, and a first top contact positioned over and in contact with the top portion of the first channel structure.

Abstract: A semiconductor structure includes one or more first nanostructures extending along a first lateral direction; one or more second nanostructures extending along the first lateral direction and vertically disposed above the one or more first nanostructures; and a gate structure extending along a second lateral direction perpendicular to the first lateral direction, and disposed around each of the one or more first nanostructures and each of the one or more second nanostructures. The gate structure comprises: (i) a first metal material, (ii) a ferroelectric material, and (iii) a second metal material.

Abstract: A semiconductor device includes a substrate having a substrate surface, a transistor stack provided on the substrate surface and including a plurality of transistors stacked on each other along a vertical direction that is perpendicular to the substrate surface. Each transistor in the transistor stack includes a vertical channel structure extending along the vertical direction and having a first vertical sidewall and a second vertical sidewall opposite to the first vertical sidewall, and a ferroelectric gate structure in contact with the first vertical sidewall of the vertical channel structure; and a back gate structure provided on the substrate and in contact with the second vertical sidewall of the vertical channel structure of each respective transistor in the transistor stack.

Abstract: Aspects of the present disclosure provide a semiconductor structure, which can include a lower transistor including a lower channel that is elongated horizontally and includes a lower doped first-type semiconductor layer of a lower doped semiconductor layer, an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally and includes an upper doped first-type semiconductor layer of an upper doped semiconductor layer, a lower capacitor electrically connected to and horizontally elongated from the lower transistor and including a first lower plate that includes a lower doped second-type semiconductor layer of the lower doped semiconductor layer, and an upper capacitor vertically stacked over the lower capacitor and electrically connected to and horizontally elongated from the upper transistor and including a first upper plate that includes an upper doped second-type semiconductor layer of the upper doped semiconductor layer.

Abstract: Aspects of the present disclosure provide 3D semiconductor apparatus and a method for fabricating the same. The 3D semiconductor apparatus can include a first semiconductor device including first S/D regions, a first gate region sandwiched by the first S/D regions, and a first channel surrounded by the first S/D regions and the first gate region; a second semiconductor device stacked on the first semiconductor device that includes second S/D regions, a second gate region sandwiched by the second S/D regions, and a second channel surrounded by the second S/D regions and the second gate region and formed vertically in-situ on the first channel; and silicide formed between the first and second semiconductor devices where the first and second channels interface and coupled to an upper one of the first S/D regions of the first semiconductor device and a lower one of the second S/D regions of the second semiconductor device.

Abstract: Microfabrication of a collection of transistor types on multiple transistor planes in which both HV (high voltage transistors) and LV (low-voltage transistors) stacks are designed on a single substrate. As high voltage transistors require higher drain-source voltages (Vds), higher gate voltages (Vg), and thus higher Vt (threshold voltage), and relatively thicker 3D gate oxide thicknesses, circuits made as described herein provide multiple different threshold voltages devices for both low voltage and high voltage devices for NMOS and PMOS, with multiple different gate oxide thickness values to enable multiple transistor planes for 3D devices.

Abstract: Aspects of the present disclosure provide a floating body vertical field effect transistor with dielectric core and a method for fabricating the same. The floating body vertical field effect transistor can include a first semiconductor device including sidewall structures of a first gate metal sandwiched by dielectric layers, a first epitaxially grown channel surrounded by the sidewall structures and can include a second semiconductor device formed on the same substrate adjacent to the first semiconductor device; a salicide layer or doped layer formed between the first and second semiconductor devices and metallization contacting each of the S/D regions and the gate regions. The floating body vertical field effect transistor may include a P+ epitaxially grown channel formed on the same substrate adjacent to an N+ epitaxially grown channel, the P+ epitaxially grown channel separated from N+ epitaxially grown channel by a diffusion break.

Abstract: Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower transistor including a lower channel that is elongated horizontally, and an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally. The semiconductor structure can also include a lower metal capacitor electrically connected to and horizontally elongated from the lower transistor. The lower metal capacitor can include a first lower metal plate that is in-plane with the lower channel of the lower transistor. The semiconductor structure can also include an upper metal capacitor vertically stacked over the lower metal capacitor and electrically connected to and horizontally elongated from the upper transistor. The upper metal capacitor can include a first upper metal plate that is in-plane with the upper channel of the upper transistor. method for improving overlay alignment of patterning by correcting wafer shape.

Abstract: A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. At least one DRAM cell unit includes a transistor and a capacitor. The capacitor includes a first metal layer, a capacitor dielectric layer positioned on the first metal layer, and a second metal layer positioned on the capacitor dielectric layer. The capacitor is elongated in a horizontal direction parallel to the working surface of the substrate. The second metal layer has a first end and a second end in the horizontal direction. The transistor includes a channel structure, and a gate structure disposed all around the channel structure. The first metal layer extends in the horizontal direction beyond the first end of the second metal layer to form a drain region and a source region of the transistor.

Abstract: Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower transistor including a lower channel that is elongated horizontally; an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally; a lower metal capacitor electrically connected to and horizontally elongated from the lower transistor, the lower metal capacitor including a first lower metal plate, a lower dielectric layer that surrounds the first lower metal plate, and a second lower metal plate that surrounds the lower dielectric layer; and an upper metal capacitor vertically stacked over the lower metal capacitor and electrically connected to and horizontally elongated from the upper transistor, the upper metal capacitor including a first upper metal plate, an upper dielectric layer that surrounds the first upper metal plate, and a second upper metal plate that surrounds the upper dielectric layer.

Abstract: A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction. At least one DRAM cell unit includes a transistor and a capacitor. The capacitor includes a first metal layer, a capacitor dielectric layer on the first metal layer, and a second metal layer on the capacitor dielectric layer. The capacitor is elongated in a horizontal direction. The first metal layer has a first end and a second end in the horizontal direction. The transistor includes a channel structure, and a gate structure on the channel structure. The second metal layer extends in the horizontal direction beyond the first end of the first metal layer to form a drain region and a source region of the transistor. A common ground structure is configured to electrically connect to a plurality of first metal layers on respective second ends.

Abstract: A semiconductor device includes a memory cell unit positioned over a substrate. The memory cell unit includes a transistor and a capacitor. The capacitor includes an inner conductor, a capacitor dielectric all around the inner conductor, an outer conductor all around the capacitor dielectric, and dielectric support structures below the inner conductor. The capacitor is elongated in a length direction parallel to a working surface of the substrate, and the dielectric support structures are spaced along the length direction. The transistor includes a channel structure, a gate structure all around the channel structure, and source/drain (S/D) regions on opposing ends of the channel structure.

Abstract: Aspects of the present disclosure provide a method for forming a semiconductor structure having separated vertical channel structures. The method can include forming a layer stack on a substrate, the layer stack including alternating metal layers and dielectric layers. The method can further include forming vertically stacked lower and upper vertical channel structures vertically extending through the layer stack, the lower and upper vertical channel structures being separated by a sacrificial layer. The method can further include forming source, drain and gate connections to the lower and upper vertical channel structures, the source, drain and gate connections extending horizontally from the lower and upper vertical channel structures and then vertically to a location above the upper vertical channel structure.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack of channel layers positioned over a substrate, where the channel layers are spaced apart from one another. The semiconductor device includes source/drain (S/D) structures positioned at a first side and a second side of the stack of channel layers and in contact with the channel layers, where the first side is opposite to the second side. The semiconductor device includes gate dielectric layers arranged around the channel layers, and gate electrodes surrounding the gate dielectric layers and further extending from a third side and a fourth side of the stack of channel layers, where the third side is opposite to the fourth side. The semiconductor device further includes a seed layer positioned over the stack of channel layers.

Abstract: One or more 3D VFET structures with 2D material based channels using a wafer transfer technology and a metal first approach are disclosed. Transistor devices can be formed, where each transistor can include an elongate structure extending vertically from a first/source drain contact, a first end of the elongate structure in electrical contact with the first source/drain contact and a second end of the elongate structure in electrical contact with a second source/drain contact. The transistor can also include a channel that includes a 2D material layer extending along an external surface of the elongate structure and a gate structure including a high-k dielectric extending along the 2D material and a gate metal in contact with the high-k dielectric. The 2D material can laterally surround the elongate structure and the gate structure can surround the 2D material.

Abstract: A method for fabricating semiconductor devices, may include forming a dielectric having a central portion with top and bottom surfaces thereof. A first sacrificial material and a second sacrificial material may be formed on the top and bottom surfaces, respectively, of the dielectric. End portions of the dielectric may be replaced with a first source/drain (S/D) metal and a second S/D metal. The central portion of the dielectric may be exposed at least by removing the first sacrificial material and second sacrificial material.

Abstract: Methods for the manufacture of semiconductor devices constructed with three-dimensional (3D) single crystal silicon nano sheets integrated with two-dimensional (2D) materials are disclosed. A device may include a semiconductor material and having a first end and a second end doped with a first polarity; a seed material wrapping around the semiconductor material; a two-dimensional (2D) material around the seed material; an active gate around the 2D material; and a source/drain structure in contact with the first end and the second end of the semiconductor material and in contact with the 2D material, wherein the source/drain structure is doped with a second polarity opposite to the first polarity.