Abstract: A method includes receiving a first device wafer comprising a plurality of dies, bonding a first side of a temporary wafer to a first side of the first device wafer to form a combined wafer, and performing a first patterning process on the combined wafer to form first trenches in the combined wafer. The first trenches fully extend through the first device wafer and partially into the temporary wafer from the first side of the temporary wafer. The first trenches separate the plurality of dies from each other. The method further includes placing the combined wafer on a support and applying a force to the combined wafer to separate the temporary wafer into individual temporary regions. Each individual temporary region is bonded to a respective individual die. The method further includes attaching individual dies to a second device wafer and removing the individual temporary regions from the individual dies.

Abstract: Structures and methods are disclosed in which a layer stack can be formed with a plurality of layers of a metal, where each of the layers of metal can be separated by a layer of a dielectric. An opening in the layer stack can be formed such that a semiconductor layer beneath the plurality of layers of the metal is uncovered. One or more vertical channel structures can be formed within the opening by epitaxial growth. The vertical channel structure can include a vertically oriented transistor. The vertical channel structure can include an interface of a silicide metal with a first metal layer of the plurality of metal layers. The interface can correspond to one of a source or a drain connection of a transistor. The silicide metal can be annealed above a temperature threshold to form a silicide interface between the vertical channel structure and the first metal layer.

Abstract: Methods for the manufacture of semiconductor devices constructed with two-dimensional (2D) materials and conductive oxides using three-dimensional (3D) nanosheets are disclosed. Aspects can include forming the stack of layers comprising a first layer of a semiconductive-behaving material separated from a base layer by a first layer of a first dielectric material and a first layer of a second dielectric material; a second layer of the semiconductive-behaving material separated from the first layer of the semiconductive-behaving material by a second layer of the second dielectric material; and a second layer of the second dielectric material formed on the second layer of the semiconductive-behaving material. Aspects include forming a metal contact coupled with the semiconductive-behaving material, forming a 2D material on the semiconductive-behaving material, forming a layer of a high-k dielectric material on the 2D material, and forming a gate metal on the high-k dielectric material.

Abstract: A semiconductor device includes a buried power rail (BPR) over a substrate and a semiconductor structure over the BPR. The semiconductor structure is tube-shaped and extends along a vertical direction. The semiconductor structure includes a first source/drain (S/D) region over the BPR, a gate region over the first S/D region, and a second S/D region over the gate region. The semiconductor device includes a first S/D interconnect structure extending from the BPR and further into the semiconductor structure such that a top portion of the first S/D interconnect structure is surrounded by the first S/D region. The semiconductor device includes a gate structure that includes (i) a gate oxide formed along an inner surface of the gate region and (ii) a gate electrode formed along sidewalls of the gate oxide in the gate region. The semiconductor device includes a second S/D interconnect structure positioned over the second S/D region.

Abstract: Example implementations can include a device with a core including a first dielectric material, the core having a mesa structure, a first layer disposed over opposite faces of the mesa structure of the core, the first layer including a metal material, and a second layer disposed over the mesa structure of the core and the first layer, the second layer including a two-dimensional material. Example implementations can include a method of manufacturing a stackable semiconductor device with a two-dimensional material layer, by depositing, over a substrate, a base layer including a first dielectric material, forming, on the base layer, at least one core having a mesa structure, forming sidewalls on opposite vertical surfaces of the mesa structure of the core, depositing, over the core and the sidewalls, a semiconductor layer including a two-dimensional material, and encapsulating the core, the sidewalls, and the semiconductor layer.

Abstract: A method of microfabrication includes epitaxially growing a first vertical channel structure of silicon-containing material on a first sacrificial layer of silicon containing material, the first sacrificial layer having etch selectivity with respect to the vertical channel structure. A core opening is directionally etched through the vertical channel structure to expose the first sacrificial layer, and the first sacrificial layer is isotropically etched through the core opening to form a first isolation opening for isolating the first vertical channel structure.

Abstract: Three-dimensional (3D) memory structures and methods to manufacture 3D memory structures are disclosed. A method includes forming a stack of layers including a first sub-stack for a first transistor structure, comprised of a first conductive layer, a gate layer, and a second source/drain layer. The stack of layers can include a second sub-stack for a memory structure positioned on the first sub-stack, the second sub-stack including at least one layer of conductive material and at least one layer of non-conductive material, and a third sub-stack for a second transistor structure. The method includes forming a channel opening in the stack of layers, providing a first channel structure within the channel opening, forming a memory dielectric layer in the channel opening and aligned with the memory structure, and providing a second channel structure in the channel opening in contact with the memory dielectric layer and aligned with the second transistor structure.

Abstract: Methods and devices are described for electronic devices, such as memory elements. In some implementations, the device may include a first layer including a source region, a drain region and a channel between the source region and drain region, the source and drain being in the same or different plane than at least a portion of the channel. In addition, the device may include a gate dielectric on the first layer and in contact with the channel, a first conductor on the gate dielectric, a ferroelectric layer on the first conductor, and a second conductor material on the ferroelectric layer. The gate structure may be utilized as a storage capacitor for a memory element.

Abstract: Apparatuses, devices, and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

Abstract: A method of fabricating a semiconductor device includes forming on a patterned multilayered stack including sacrificial layers alternatingly stacked with channel layers on a substrate, the patterned multilayered stack having opposing sidewalls and opposing ends. Cantilever supports are formed on the substrate, each cantilever support being in contact with a respective opposing end of the patterned multilayered stack. A gate-all-around (GAA) structure is formed around each channel layer while the opposing ends of the multilayered stack are supported by the cantilever supports. The cantilever supports are removed from the opposing ends of the patterned multilayered stack to expose end portions of each channel layer, and source-drain (S-D) regions are formed on the exposed end portions of each respective channel layer.

Abstract: A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

Abstract: A microfabricated transistor device includes a vertical stack of two or more channels of field effect transistors on a semiconductor substrate. Each of the channels has a vertical conductive path relative to a surface of the semiconductor substrate. At least one of the channels includes a shell formed around a core material, the shell including epitaxial material. The vertical stack can include a channel for a PMOS field effect transistor, and a channel for an NMOS field effect transistor.

Abstract: A method of fabricating a semiconductor device includes forming a patterned stack of layers including at least one lower active layer for forming a lower transistor and at least one upper active layer for forming an upper transistor stacked on the lower transistor. A dummy gate is formed surrounding a gate portion of each of the lower active layers and each of the upper active layers in the patterned stack, and the source-drain portions of the lower active layers and the upper active layers are doped. Source-drain connections to doped source-drain portions of the lower active layers and the upper active layers are formed. The dummy gate of the lower active layers and the upper active layers is replaced with a gate-all-around (GAA) structure to form the lower transistor and the upper transistor.

Abstract: Methods for the manufacture of three-dimensional (3D) semiconductor devices are disclosed. Aspects can include forming a patterned first conductive source/drain structure of a transistor structure, forming a gate patterned conductive structure of the transistor structure separated from the first conductive source/drain structure by at least one dielectric layer, forming a patterned second conductive source/drain structure of the transistor structure separated from the gate patterned conductive structure by at least one dielectric layer, forming a transistor body opening extending through the transistor structure, forming a gate dielectric in the transistor body opening, and forming a material in the transistor body opening extending from the patterned first conductive source/drain structure to the patterned second conductive source/drain structure.

Abstract: A semiconductor device includes a substrate having a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure including a main portion extending in a main direction along the working surface, and tail portions each connected to a respective end of the main portion and extending along the working surface in a different direction from the main direction, a distal end of each tail portion including a source-drain (S-D) end such that the S-D ends are offset from the main portion of the complex channel structure. A gate all around (GAA) structure formed around only the main portion of the complex channel structure between the tail portions, and S-D contacts formed on respective S-D ends of the complex channel structure such that the S-D contacts are offset from the GAA structure.

Abstract: In some implementations, the device may include a vertical transistor having a first source/drain (s/d) region adjacent a substrate, a channel region above the first s/d region, and a second s/d region. In addition, the device includes a capacitor having two conductive regions separated by a dielectric region, one of the two conductive regions electrically coupled to the second s/d region.

Abstract: A method of microfabrication is provided. The method includes forming shell structures above a first layer including a first semiconductor material. The shell structures are electrically isolated from each other and electrically isolated from the first layer. The shell structures include at least one type of semiconductor material and each include a dielectric core structure. Each shell structure is configured to include a top source/drain (S/D) region, a channel region and a bottom S/D region serially connected in a vertical direction perpendicular to the first layer and have a current flow path in the vertical direction. A bottom contact structure connected to a respective bottom S/D region of each shell structure is formed. A gate structure is formed on a sidewall of a respective channel region of each shell structure.

Abstract: A memory element and method of formation is disclosed that includes a transistor integrated with a capacitor through a common nanosheet. The transistor includes a channel, a source region, a drain region and a gate component on at least one side of the channel between the source region and drain region. The channel is formed in a first portion of a nanosheet. The capacitor has a first capacitor component and second capacitor component separated by an insulator. The first capacitor component is provided in a second portion of the nanosheet.

Abstract: Aspects of the present disclosure provide a bonding device for bonding two wafers. For example, the bonding device can include a first bonding chuck and a second bonding chuck. The first bonding chuck can have a first bonding head for a first wafer to be mounted thereon. The second bonding chuck can have a plurality of second bonding heads for a second wafer to be mounted thereon. The second bonding heads can be controlled individually to apply local pressures onto the second wafer to move the second wafer toward the first wafer to bond the second wafer to the first wafer, the local pressures corresponding to bow measurement of the first wafer and the second wafer.

Abstract: Apparatuses, devices and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.