Abstract: Aspects of the present disclosure provide 3D semiconductor structures and methods for fabricating the same. For example, the method can include forming a first multilayer stack over a substrate, forming a second multilayer stack over the first multilayer stack, forming a first opening through the first and second multilayer stack until uncovering a top surface of the substrate, forming in the first opening a first vertical field-effect transistor (VFET) over the substrate, and forming in the first opening a second VFET over the first VFET. The first VFET can include a first channel having a first length corresponding to a first thickness of a first layer of the first multilayer stack. The second VFET can include a second channel having a second length corresponding to a second thickness of a second layer of the second multilayer stack. The second thickness can be different from the first thickness.

Abstract: Aspects of the present disclosure provide a 3D semiconductor structure and a method for fabricating the same. The 3D semiconductor structure can include a vertical field-effect transistor (VFET). The VFET can include a lower source/drain (S/D) region, a channel formed on the lower S/D region, a gate region surrounding the channel, and an upper S/D region formed on the channel. One of the lower and upper S/D regions can include a channel material having a graded dopant profile. The VFET can further include lower and upper S/D electrodes coupled to the lower and upper S/D regions, respectively, a gate electrode coupled to the gate region, a lower S/D spacer formed between the lower S/D electrode and the gate electrode, and an upper S/D spacer formed between the gate electrode and the upper S/D electrode. The upper S/D spacer can have a different thickness from the lower S/D spacer.

Abstract: A semiconductor device may include a first dielectric layer, a first gate electrode, a first gate dielectric layer, a first source electrode, a first drain electrode, and a first two-dimensional (2D) semiconductor layer. The first dielectric layer may have a first top surface. The first gate electrode may extend from the first top surface into the first dielectric layer. The first gate dielectric layer may be disposed on the first gate electrode and have a second top surface. The first source electrode may extend from the second top surface, through the first gate dielectric layer and into the first dielectric layer. The first drain electrode may extend from the second top surface, through the first gate dielectric layer and into the first dielectric layer. The first 2D semiconductor layer may be disposed on the first gate dielectric layer.

Abstract: Example implementations can include a device with a core including a first dielectric material, the core having a mesa structure, a first layer disposed over opposite faces of the mesa structure of the core, the first layer including a metal material, and a second layer disposed over the mesa structure of the core and the first layer, the second layer including a two-dimensional material. Example implementations can include a method of manufacturing a stackable semiconductor device with a two-dimensional material layer, by depositing, over a substrate, a base layer including a first dielectric material, forming, on the base layer, at least one core having a mesa structure, forming sidewalls on opposite vertical surfaces of the mesa structure of the core, depositing, over the core and the sidewalls, a semiconductor layer including a two-dimensional material, and encapsulating the core, the sidewalls, and the semiconductor layer.

Abstract: The disclosed technology generally relates to a process of forming transistors with high-k dielectric layers, such as selectively high-k dielectric layers. The high-k dielectric layers, which may be used as the gate dielectric, may be selectively grown from two-dimensional semiconductor materials. The process may be adapted for various transistor structures such as planar transistors, three-dimensional transistors, and gate-all-around transistors. Further, the process may also be used to create stacked transistors. In one aspect, a method for manufacturing a semiconductor device includes forming a seed structure over a base layer, forming a two-dimensional (2D) semiconductor layer disposed on the seed structure, and selectively growing a high-k dielectric layer over the 2D semiconductor layer.

Abstract: Apparatuses, devices and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

Abstract: In a semiconductor device, a device structure is positioned over a substrate, where the device structure includes devices. A wiring structure of the semiconductor device is positioned over the substrate and coupled to at least one of the devices. The wiring structure includes at least one of programmable lines and programmable vertical interconnects, where the programmable lines extend along a top surface of the substrate and the programmable vertical interconnects extend along a vertical direction perpendicular to the top surface of the substrate. The programmable lines and the programmable vertical interconnects include a programmable material having a modifiable resistivity in that the programmable lines and the programmable vertical interconnects change between being conductive and being non-conductive in responsive to a current pattern delivered to the programmable lines and the programmable vertical interconnects.

Abstract: Aspects of the present disclosure provide a vertical channel 3D semiconductor device sand a method for fabricating the same. The 3D semiconductor devices may have vertical channels of the same or different epitaxially grown doped materials. Sidewall structures are formed around each vertical channel by masking and etching material between the vertical channels. A dielectric layer in each of the sidewalls is etched down to the vertical channel and a gate electrode structure is formed in the opening. The gate electrode structure may include an interfacial oxide, a high-K layer and alternating metal layers. Local interconnects connect to the metal of the gate structure.

Abstract: A method of forming a vertical channel transistor includes forming a first source-drain (SD) contact on a semiconductor substrate, depositing a layer of vertical channel core material on the first SD contact and depositing a layer of second SD contact material on the layer of channel core material. Also included is pattern etching the layer of second SD contact material and the layer of channel core material to form a vertical channel core having a first end connected to the first SD contact and a second end opposite to the first end and connected to a second SD contact formed by the etching the layer of second SD contact material. A vertical channel structure is formed on a sidewall of the vertical channel core, and a gate-all-around (GAA) structure is formed to completely surrounding at least a portion of the vertical channel structure.

Abstract: A semiconductor device includes a substrate, a first wiring layer over the substrate, and a first array of transistor pairs extending over the first wiring layer. Cross sections of each transistor pair cut through the first array. The cross sections of each transistor pair have a similar structure. Each transistor pair includes a mandrel having two opposite sidewalls that are perpendicular to the substrate and extending along a direction of the first array of transistor pairs. Each transistor pair includes two transistors symmetrically disposed over the two opposite sidewalls of the respective mandrel.

Abstract: A method of fabricating a semiconductor device includes receiving a first wafer including a first substrate on a backside of the first wafer, and a first semiconductor-on-insulator (SOI) stack on a front side of the first wafer. The first SOI stack includes a first semiconductor. A second wafer is received that includes a second substrate on a backside of the second wafer, and a second SOI stack on a front side of the second wafer. The second SOI stack includes a second semiconductor. The front side of the first wafer is bonded to the front side of the second wafer, via at least one dielectric bonding material, to form a bonded wafer. The second substrate is removed. A stack of transistor devices is formed with the first semiconductor used as a first channel for a first transistor and the second semiconductor used as a second channel for a second transistor.

Abstract: A method of forming a vertical channel transistor includes forming a first source-drain (SD) contact on a first surface of a semiconductor device layer; and forming a second SD contact layer on a second surface of the semiconductor device layer, the second surface being opposite to the first surface. The semiconductor device layer is pattern etched to form a vertical channel structure having a first end connected to the first SD contact and a second end opposite to the first end and connected to the second SD contact. A gate-all-around (GAA) structure is formed to completely surrounding at least a portion of the vertical channel structure at a position between the first SD contact and the second SD contact.

Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. The method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method can further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

Abstract: Three-dimensional (3D) memory structures and methods to manufacture 3D memory structures are disclosed. A method includes forming a stack of layers including a first sub-stack for a first transistor structure, comprised of a first conductive layer, a gate layer, and a second source/drain layer. The stack of layers can include a second sub-stack for a memory structure positioned on the first sub-stack, the second sub-stack including at least one layer of conductive material and at least one layer of non-conductive material, and a third sub-stack for a second transistor structure. The method includes forming a channel opening in the stack of layers, providing a first channel structure within the channel opening, forming a memory dielectric layer in the channel opening and aligned with the memory structure, and providing a second channel structure in the channel opening in contact with the memory dielectric layer and aligned with the second transistor structure.

Abstract: Three-dimensional (3D) NAND memory structures and methods to manufacture 3D NAND memory structures are disclosed. A method includes forming a stack of layers that includes a first sub-stack for a transistor structure and a second sub-stack for a memory structure positioned on the first sub-stack. The second sub-stack includes at least one layer of conductive material and at least one layer of non-conductive material. The first sub-stack and the second sub-stack are separated by at least one non-conductive layer. The method includes forming a channel opening in the stack of layers, forming a gate dielectric in the channel opening, and providing a channel structure within the channel opening. The channel structure includes a semiconductive-behaving material and aligned with the transistor structure. The method includes providing a charge trap layer within the channel opening and aligned with the memory structure.

Abstract: Apparatuses, devices, and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

Abstract: A device including one or more transistors with nano sheets stacked along a vertical direction, and a method of fabricating the device are disclosed herein. In some embodiments, a device includes a transistor structure including at least a first dielectric nano sheet and a second dielectric nano sheet. The first dielectric nano sheet and the second dielectric nano sheet may extend parallel to a substrate. The second dielectric nano sheet may be disposed above the first dielectric nano sheet. The transistor may include a first source/drain structure coupled to a first end of the first dielectric nano sheet and a first end of the second dielectric nano sheet, and a second source/drain structure coupled to a second end of the first dielectric nano sheet and a second end of the second dielectric nano sheet.

Abstract: A semiconductor device includes a stack of layers, a vertical channel structure and vertical contact structures. The stack of layers defines a sidewall surface and includes terminal layers which include source, gate and drain layers. The vertical channel structure defines an inner axis that is substantially transverse to a main surface of the stack of layers. The vertical contact structures are each configured to electrically connect to a respective terminal layer. At least two vertical contact structures are in different radial positions relative to the inner axis.

Abstract: A semiconductor device includes a stack of layers defining a sidewall surface and comprising source and drain layers. A channel structure extends through the stack of layers, is oriented in a vertical direction perpendicular to a main surface of the stack of layers, and is configured to have a current flow path in the vertical direction. The channel structure includes a two-dimensional (2D) semiconductor material. A core structure is positioned inside and surrounded by the channel structure, and a gate structure surrounds at least part of the channel structure.

Abstract: Disclosed herein are related to a device including vertically placed semiconductor devices in a trench, and a method of fabricating the vertically placed semiconductor devices. In one aspect, a device includes a substrate including a trench defined by a first sidewall and a second sidewall facing each other along a first direction, and a floor between one end of the first sidewall and one end of the second sidewall. The device may include two or more vertical slots separated by vertical nano sheets extending upwards from the floor within the trench. In one aspect, the semiconductor devices can be formed in the two or more vertical slots. For example, source/drain structures, gate structures, and additional source/drain structures of vertical transistors can be formed in the two or more vertical slots.