Patents by Inventor Mark J. Foster

Mark J. Foster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5557500
    Abstract: A heat dissipating arrangement in a portable computer uses a copper slug disposed between a heat-generating central processing unit (CPU) chip and the underside of a metallic keyboard baseplate. The slug also extends through a copper-plated hole in a printed circuit (PC) board, and is either soldered to the copper plating or press-fit into the hole to enhance heat transfer between the slug and the PC board. Small through-holes extend through the PC board and the copper plating next to the opening. These through-holes connect the copper plating to several layers of etch within the PC board, so that these layers act like fins on a heat sink to increase heat transfer away from the CPU.
    Type: Grant
    Filed: December 7, 1994
    Date of Patent: September 17, 1996
    Assignee: Digital Equipment Corporation
    Inventors: Allan S. Baucom, Mark J. Foster, Michele Bovio
  • Patent number: 5551033
    Abstract: A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. The system includes a first interrupt mask register having a bit for indicating whether an interrupt is to be recognized by the processor, a second interrupt mask register having a bit for indicating whether the interrupt is to be recognized by a further circuit, and an arrangement responsive to a load of the first mask register for conforming the bit of the second mask register to the bit of the first mask register in a manner invisible to an application program being executed by the processor.
    Type: Grant
    Filed: June 4, 1992
    Date of Patent: August 27, 1996
    Assignee: Zenith Data Systems Corporation
    Inventors: Mark J. Foster, Saifuddin T. Fakhruddin, James L. Walker, Matthew B. Mendelow, Jiming Sun, Rodman S. Brahman, Michael P. Krau, Brian D. Willoughby, Michael D. Maddix, Steven L. Belt, Scott A. Hovey, Mark A. Ruthenbeck
  • Patent number: 5394527
    Abstract: A computer system has a processing unit with suspend/resume capability, a memory, and a hard disk drive. In response to a first command from the processor, the hard disk drive sends its status to the processor and the processor stores it in the memory. In response to a second command from the processor, the hard disk accepts from the processor the status retrieved by the processor from the memory, and restores itself to this status. In an alternative embodiment, the hard disk drive response to the first command by storing its status on its own hard disk, and responds to the second command by restoring this status from the hard disk. In each case, an output line from the hard disk used to control a light emitting diode is also selectively used to create an interrupt to the processor which facilitates the systems entry into the suspend mode.
    Type: Grant
    Filed: October 26, 1993
    Date of Patent: February 28, 1995
    Assignee: Zenith Data Systems Corporation
    Inventors: Saifuddin T. Fakhruddin, Mark J. Foster, Scott A. Hovey, James L. Walker, Randy J. Vanderheyden
  • Patent number: 5280621
    Abstract: A plurality of processors form a network used to communicate with one or more peripheral devices and the system control processor. One processor is dedicated to at least one peripheral device. Since the system control processor is not burdened with the relatively slow communications protocol with the peripheral devices, it is free to do other tasks which improves the overall system performance. Communication protocol between the dedicated processors allows for local and global communication.
    Type: Grant
    Filed: February 17, 1993
    Date of Patent: January 18, 1994
    Assignee: Zenith Data Systems Corporation
    Inventors: Brian C. Barnes, Mark J. Foster, Lloyd W. Gauthier, Saifee Fakhruddin, David J. DeLisle, David R. Veit
  • Patent number: 5253350
    Abstract: In response to an address decoded in a preselected range, a multiplexer combines translated high order address bits with CPU-generated low order address bits to access random access memory, especially reserved range random access memory. Otherwise, the multiplexer merely combines CPU-generated low order bits with CPU-generated high order address bits to access RAM. An expanded memory specification memory map drives the translator to generate the translated high order address bits. This generates the address for reserved range RAM. RAM contents, normal and reserved range, are available for processing by the CPU.
    Type: Grant
    Filed: July 19, 1990
    Date of Patent: October 12, 1993
    Assignee: Zenith Data Systems Corporation
    Inventors: Mark J. Foster, Babu Rajaram, Anthony M. Olson
  • Patent number: 5157776
    Abstract: A method and main memory system that provides a processor cache includes. Dual-port random access memory devices used for main memory, with one port providing typical random access and a second port being associated with an internal shift register that contains sequential instruction words. Improved system speed can be achieved by virtue of the shorter access time of the second port. A preferred embodiment is adapted to employ conventional video random access memory devices as constituents of a main memory system with unique control methods.
    Type: Grant
    Filed: October 23, 1989
    Date of Patent: October 20, 1992
    Assignee: Zenith Data Systems Corporation
    Inventor: Mark J. Foster
  • Patent number: 5136694
    Abstract: A computing device includes a system control processor, a built-in keyboard having a plurality of keys, a connector which facilitates connection of an external keyboard or keypad to the device, an electronic switch which is controlled by the internal keyboard processor and can electrically couple the connector to the system control processor. The internal keyboard processor monitors signals from the system control processor, connector and internal keyboard keys in order to open and close the analog switch so as to facilitate transfers between the system control processor and the internal keyboard through itself, and transfers between the system control processor and an external keyboard through the electronic switch.
    Type: Grant
    Filed: April 7, 1989
    Date of Patent: August 4, 1992
    Assignee: Zenith Data Systems Corporation
    Inventors: Steven L. Belt, Mark A. Ruthenbeck, Mark J. Foster, Brian C. Barnes, Randy J. VanderHeyden
  • Patent number: 5027294
    Abstract: A method and apparatus for monitoring the voltage discharge of a battery power supply while under load, and to manage the power supply by accurately calculating the time the useful charge is nearly depleted, providing a series of warnings to the user-operator of that fact, and subsequently performing a system shutdown before a complete discharge of the battery. If the invention is applied to a battery power supply for a computer, the series of warnings enable the computer operator to transfer data from a temporary memory to permanent storage in the time interval between a warning signal and computer shutdown; and since computer shutdown is effected before the battery is fully discharged a battery-destructive phenomenon known as a polarity cell reversal is prevented.
    Type: Grant
    Filed: January 27, 1989
    Date of Patent: June 25, 1991
    Assignee: Zenith Data Systems Corporation
    Inventors: Saifee Fakruddin, Mark J. Foster
  • Patent number: 4984209
    Abstract: An improved method for refreshing dynamic random access memory devices is disclosed. Normal refresh clocking signals are monitored and a count accumulated up to a selected value. Refresh operations are then initiated less frequently and only when the selected count has been accumulated. Once control of the bus to the memory has been achieved, a burst of refresh operations are performed prior to release of the bus. Improved efficiency and operating speed may be achieved by minimizing wasted time associated with acquisition and control of the bus. A preferred embodiment illustrates savings associated with a burst of four refresh operations each time the bus to the memory device is acquired for refreshing. Page addressing techniques are enhanced by forcing a change of state of the row address strobe line bus frequently than typical refresh operations.
    Type: Grant
    Filed: October 30, 1987
    Date of Patent: January 8, 1991
    Assignee: Zenith Data Systems Corporation
    Inventors: Babu Rajaram, Mark J. Foster
  • Patent number: 4744046
    Abstract: Paging and scrolling is provided in a video display terminal having a multi-page video memory by restricting memory access when in the scrolling mode to the page being displayed. An address pager functions as a multiplexer in coupling a central processing unit (CPU) and a cathode ray tube (CRT) controller to the video memory allowing the CPU to designate the mode of operation (paging or scrolling) and the page in memory to be addressed in the scrolling mode of operation, and permits the CRT controller to designate page as well as location to be addressed therein in the paging mode of operation. By limiting display access only to memory locations within a given page while in the scrolling mode, the overlapping and overwriting of adjacent pages of the video memory is avoided.
    Type: Grant
    Filed: November 2, 1984
    Date of Patent: May 10, 1988
    Assignee: Zenith Electronics Corporation
    Inventor: Mark J. Foster
  • Patent number: 4714919
    Abstract: Smooth scrolling is provided in a video display terminal having a cathode ray tube (CRT) controller which, by itself, is only capable of discontinuous, jump scrolling. The start-of-display address modification technique of advancing the start-of-display a single row at a time is combined with a display vertical position control normally used for changing the position of the display on the CRT faceplate. By sequentially erasing the top scan line, moving the entire display up one scan line by means of the vertical position control, erasing the second scan line, restoring the vertical position control to its original value, and advancing the CRT controller start address by two scan lines, the character rows are scrolled upward in a smooth, continuous manner. This sequence of operations is repeated a predetermined number of times for each character line with the "wrap-around" feature of a video memory used to provide new information for the bottom scan line.
    Type: Grant
    Filed: July 30, 1984
    Date of Patent: December 22, 1987
    Assignee: Zenith Electronics Corporation
    Inventor: Mark J. Foster
  • Patent number: D366256
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: January 16, 1996
    Assignee: Digital Equipment Corporation
    Inventors: Christian C. Landry, Robert T. Faranda, Michele Bovio, Mark J. Foster
  • Patent number: D370666
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: June 11, 1996
    Assignee: Digital Equipment Corporation
    Inventors: Michele Bovio, Robert T. Faranda, Mark J. Foster