Abstract: A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) includes a source/drain region comprising a first III-V compound semiconductor material, and a contact plug over and connected to the source/drain region. The contact plug includes a second III-V compound semiconductor material.

Abstract: A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.

Abstract: A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.

Abstract: A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.

Abstract: A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.

Abstract: Integrated circuit devices having FinFETs with channel regions low in crystal defects and current-blocking layers underneath the channels to improve electrostatic control. Optionally, an interface control layer formed of a high bandgap semiconductor is provided between the current-blocking layer and the channel. The disclosure also provides methods of forming integrated circuit devices having these structures. The methods include forming a FinFET fin including a channel by epitaxial growth, then oxidizing a portion of the fin to form a current-blocking layer.

Abstract: A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.

Abstract: A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside passivation layer disposed over the buffer layer and a channel layer disposed over the channel backside passivation layer. A gate insulator layer is disposed over and in contact with the channel layer and the channel backside passivation layer. The buffer layer optionally comprises aluminum and the channel layer may optionally comprise a III-V semiconductor compound. STIs may be disposed on opposite sides of the channel backside passivation layer, and the channel backside passivation layer may have a top surface disposed above the top surface of the STIs and a bottom surface disposed below the top surface of the STIs.

Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor strip is between and contacting the isolation regions. A semiconductor fin overlaps, and is joined to, the semiconductor strip. A ditch extends from a top surface of the isolation regions into the isolation regions, wherein the ditch adjoins the semiconductor fin.

Abstract: A device includes a wafer substrate having at least two isolation features, a buffer layer embedded between the two isolation features and a fin disposed over the buffer layer. The buffer layer includes a first lattice constant. The fin includes at least one pair of alternating layers having a compressive strained layer and a tensile strained layer such that the pair of alternating layer has a second lattice constant matching to the first lattice constant and remains strained at edge of the fin. The device further includes a gate disposed over the fin. The buffer layer, the compressive strained layer, and the tensile strained layer include element in Group III-V, or combination thereof. A thickness of the compressive strained layer or a thickness of the tensile strained layer is a function of the first lattice constant.

Abstract: A device includes a semiconductor substrate, and a channel region of a transistor over the semiconductor substrate. The channel region includes a semiconductor material. An air gap is disposed under and aligned to the channel region, with a bottom surface of the channel region exposed to the air gap. Insulation regions are disposed on opposite sides of the air gap, wherein a bottom surface of the channel region is higher than top surfaces of the insulation regions. A gate dielectric of the transistor is disposed on a top surface and sidewalls of the channel region. A gate electrode of the transistor is over the gate dielectric.

Abstract: The present disclosure describes a layout for stress optimization. The layout includes a substrate, at least two fin field effect transistors (FinFET) cells formed in the substrate, a FinFET fin designed to cross the two FinFET cells, a plurality of gates formed on the substrate, and an isolation unit formed between the first FinFET cell and the second FinFET cell. The two FinFET cells include a first FinFET cell and a second FinFET cell. The FinFET fin includes a positive charge FinFET (Fin PFET) fin and a negative charge FinFET (Fin NFET) fin. The isolation unit isolates the first FinFET cell from the second FinFET cell without breaking the FinFET fin.

Abstract: Among other things, a semiconductor device comprising one or more faceted surfaces and techniques for forming the semiconductor device are provided. A semiconductor device, such as a finFET, comprises a fin formed on a semiconductor substrate. The fin comprises a source region, a channel, and a drain region. A gate is formed around the channel. A top fin portion of the fin is annealed, such as by a hydrogen annealing process, to create one or more faceted surfaces. For example the top fin portion comprises a first faceted surface formed adjacent to a second faceted surface at an angle greater than 90 degrees relative to the second faceted surface, which results in a reduced sharpness of a corner between the first faceted surface and the second faceted surface. In this way, an electrical field near the corner is substantially uniform to electrical fields induced elsewhere within the fin.

Abstract: A device includes a wafer substrate having at least two isolation features, a buffer layer embedded between the two isolation features and a fin disposed over the buffer layer. The buffer layer includes a first lattice constant. The fin includes at least one pair of alternating layers having a compressive strained layer and a tensile strained layer such that the pair of alternating layer has a second lattice constant matching to the first lattice constant and remains strained at edge of the fin. The device further includes a gate disposed over the fin. The buffer layer, the compressive strained layer, and the tensile strained layer include element in Group III-V, or combination thereof. A thickness of the compressive strained layer or a thickness of the tensile strained layer is a function of the first lattice constant.

Abstract: A method is described what includes providing a substrate having a first trench and a second trench. An epitaxy material (crystalline material) is formed in the first trench and in the second trench. The top surface of the epitaxy material in the first trench is noncollinear with a top surface of the epitaxy material in the second trench. An amorphous semiconductor layer is formed on the crystalline material. Subsequently, the amorphous layer is converted, in part or in whole, into the crystalline semiconductor material. In an embodiment, a planarization process after the conversion provides crystalline regions having a coplanar top surface.

Abstract: The present disclosure describes a layout for stress optimization. The layout includes a substrate, at least two fin field effect transistors (FinFET) cells formed in the substrate, a FinFET fin designed to cross the two FinFET cells, a plurality of gates formed on the substrate, and an isolation unit formed between the first FinFET cell and the second FinFET cell. The two FinFET cells include a first FinFET cell and a second FinFET cell. The FinFET fin includes a positive charge FinFET (Fin PFET) fin and a negative charge FinFET (Fin NFET) fin. The isolation unit isolates the first FinFET cell from the second FinFET cell without breaking the FinFET fin.

Abstract: A device includes a first source/drain region of a first conductivity type over a silicon substrate, wherein the first source/drain region is at a higher step of a two-step profile. The first source/drain region includes a germanium-containing region. A second source/drain region is of a second conductivity type opposite the first conductivity type, wherein the second source/drain region is at a lower step of the two-step profile. A gate dielectric includes a vertical portion in contact with a side edge the silicon substrate, and a horizontal portion in contact with a top surface of the silicon substrate at the lower step. The horizontal portion is connected to a lower end of the vertical portion. A gate electrode is directly over the horizontal portion, wherein a sidewall of the gate electrode is in contact with the vertical portion of the gate dielectric.

Abstract: A semiconductor device comprises a semiconductor substrate; a channel layer of at least one III-V semiconductor compound above the semiconductor substrate; a gate electrode above a first portion of the channel layer; a source region and a drain region above a second portion of the channel layer; and a dopant layer comprising at least one dopant contacting the second portion of the channel layer.

Abstract: A device includes a semiconductor substrate, and a channel region of a transistor over the semiconductor substrate. The channel region includes a semiconductor material. An air gap is disposed under and aligned to the channel region, with a bottom surface of the channel region exposed to the air gap. Insulation regions are disposed on opposite sides of the air gap, wherein a bottom surface of the channel region is higher than top surfaces of the insulation regions. A gate dielectric of the transistor is disposed on a top surface and sidewalls of the channel region. A gate electrode of the transistor is over the gate dielectric.

Abstract: A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.