Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device includes a substrate, the substrate having a first source/drain feature and a second source/drain feature formed thereon. The semiconductor device further includes a first nanowire on the first source/drain feature and a second nanowire on the second source/drain feature, the first nanowire extending vertically from an upper surface of the first source/drain feature and the second nanowire extending vertically from an upper surface of the second source/drain feature. The semiconductor device further includes a third nanowire extending from an upper end of the first nanowire to an upper end of the second nanowire, wherein the first nanowire, the second nanowire and the third nanowire form a channel.

Abstract: Among other things, a semiconductor device comprising one or more faceted surfaces and techniques for forming the semiconductor device are provided. A semiconductor device, such as a finFET, comprises a fin formed on a semiconductor substrate. The fin comprises a source region, a channel, and a drain region. A gate is formed around the channel. A top fin portion of the fin is annealed, such as by a hydrogen annealing process, to create one or more faceted surfaces. For example the top fin portion comprises a first faceted surface formed adjacent to a second faceted surface at an angle greater than 90 degrees relative to the second faceted surface, which results in a reduced sharpness of a corner between the first faceted surface and the second faceted surface. In this way, an electrical field near the corner is substantially uniform to electrical fields induced elsewhere within the fin.

Abstract: Semiconductor devices and methods of forming the same are provided. A template layer is formed on a substrate, the template layer having a recess therein. A plurality of nanowires is formed in the recess. A gate stack is formed over the substrate, the gate stack surrounding the plurality of nanowires.

Abstract: A semiconductor device and methods of formation are provided. The semiconductor device includes a first active region having a first active region height and an active channel region having an active channel region height over a fin. The first active region height is greater than the active channel region height. The active channel region having the active channel region height has increased strain, such as increased tensile strain, as compared to an active channel region that has a height greater than the active channel region height. The increased strain increases or enhances at least one of hole mobility or electron mobility in at least one of the first active region or the active channel region. The active channel region having the active channel region height has decreased source drain leakage, as compared to an active channel region that has a height greater than the active channel region height.

Abstract: A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside passivation layer disposed over the buffer layer and a channel layer disposed over the channel backside passivation layer. A gate insulator layer is disposed over and in contact with the channel layer and the channel backside passivation layer. The buffer layer optionally comprises aluminum and the channel layer may optionally comprise a III-V semiconductor compound. STIs may be disposed on opposite sides of the channel backside passivation layer, and the channel backside passivation layer may have a top surface disposed above the top surface of the STIs and a bottom surface disposed below the top surface of the STIs.

Abstract: A system and method for manufacturing a carbon layer is provided. An embodiment comprises depositing a first metal layer on a substrate, the substrate comprising carbon. A silicide is eptiaxially grown on the substrate, the epitaxially growing the silicide also forming a layer of carbon over the silicide. In an embodiment the carbon layer is graphene, and may be transferred to a semiconductor substrate for further processing to form a channel within the graphene.

Abstract: A method includes growing a nanowire from a substrate, forming a sacrificial layer surrounding the nanowire, removing the nanowire from the sacrificial layer to form an opening in the sacrificial layer, and growing a replacement semiconductor nanowire in the opening.

Abstract: The present disclosure provides a method of forming a fin-like field-effect transistor (FinFET) device. The method includes forming a first strain-relaxed buffer (SRB) stack over a substrate. The first SRB stack has a lattice mismatch with respect to the substrate that generates a threading dislocation defect feature in the first SRB stack. The method also includes forming a patterned dielectric layer over the first SRB stack. The patterned dielectric layer includes a trench extending therethrough. The method also includes forming a second SRB stack over the first SRB stack and within the trench. The second SRB stack has a lattice mismatch with respect to the substrate such that an upper portion of the second SRB stack is without threading dislocation defects.

Abstract: Among other things, a semiconductor device comprising one or more faceted surfaces and techniques for forming the semiconductor device are provided. A semiconductor device, such as a finFET, comprises a fin formed on a semiconductor substrate. The fin comprises a source region, a channel, and a drain region. A gate is formed around the channel. A top fin portion of the fin is annealed, such as by a hydrogen annealing process, to create one or more faceted surfaces. For example the top fin portion comprises a first faceted surface formed adjacent to a second faceted surface at an angle greater than 90 degrees relative to the second faceted surface, which results in a reduced sharpness of a corner between the first faceted surface and the second faceted surface. In this way, an electrical field near the corner is substantially uniform to electrical fields induced elsewhere within the fin.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device includes a substrate, the substrate having a first source/drain feature and a second source/drain feature formed thereon. The semiconductor device further includes a first nanowire on the first source/drain feature and a second nanowire on the second source/drain feature, the first nanowire extending vertically from an upper surface of the first source/drain feature and the second nanowire extending vertically from an upper surface of the second source/drain feature. The semiconductor device further includes a third nanowire extending from an upper end of the first nanowire to an upper end of the second nanowire, wherein the first nanowire, the second nanowire and the third nanowire form a channel.

Abstract: A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (STI) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate. The first semiconductor material has a first lattice constant and the second semiconductor material has a second lattice constant different from the first lattice constant. The fin-like active region further includes fluorine species.

Abstract: A semiconductor device comprises a semiconductor substrate; a channel layer of at least one III-V semiconductor compound above the semiconductor substrate; a gate electrode above a first portion of the channel layer; a source region and a drain region above a second portion of the channel layer; and a dopant layer comprising at least one dopant contacting the second portion of the channel layer.

Abstract: A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.

Abstract: A thin-sheet non-planar circuit device such as a FinFET and a method for forming the device is disclosed. In some exemplary embodiments, the device includes a substrate having a top surface and a feature disposed on the substrate that extends above the top surface. A material layer disposed on the feature. The material layer includes a plurality of source/drain regions and a channel region disposed between the source/drain regions. A gate stack is disposed on the channel region of the material layer. In some such embodiments, the feature includes a plurality of side surfaces, and the material layer is disposed on each of the side surface surfaces. In some such embodiments, the feature also includes a top surface and the material layer is further disposed on the top surface. In some embodiments, the top surface of the feature is free of the material layer.

Abstract: A system and method for manufacturing a carbon layer is provided. An embodiment comprises depositing a first metal layer on a substrate, the substrate comprising carbon. A silicide is eptiaxially grown on the substrate, the epitaxially growing the silicide also forming a layer of carbon over the silicide. In an embodiment the carbon layer is graphene, and may be transferred to a semiconductor substrate for further processing to form a channel within the graphene.

Abstract: Integrated circuit devices having FinFETs with channel regions low in crystal defects and current-blocking layers underneath the channels to improve electrostatic control. Optionally, an interface control layer formed of a high bandgap semiconductor is provided between the current-blocking layer and the channel. The disclosure also provides methods of forming integrated circuit devices having these structures. The methods include forming a FinFET fin including a channel by epitaxial growth, then oxidizing a portion of the fin to form a current-blocking layer.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (STI) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate. The first semiconductor material has a first lattice constant and the second semiconductor material has a second lattice constant different from the first lattice constant. The fin-like active region further includes fluorine species.

Abstract: A semiconductor device and methods of formation are provided. The semiconductor device includes a first active region having a first active region height and an active channel region having an active channel region height over a fin. The first active region height is greater than the active channel region height. The active channel region having the active channel region height has increased strain, such as increased tensile strain, as compared to an active channel region that has a height greater than the active channel region height. The increased strain increases or enhances at least one of hole mobility or electron mobility in at least one of the first active region or the active channel region. The active channel region having the active channel region height has decreased source drain leakage, as compared to an active channel region that has a height greater than the active channel region height.

Abstract: A semiconductor device and methods of formation are provided. The semiconductor device includes a gate over a channel portion of a fin. The fin includes a first active area of the fin having a first active area top surface coplanar with a first shallow trench isolation (STI) top surface of a first STI portion of STI, and a second active area of the fin having a second active area top surface coplanar with a second STI top surface of a second STI portion of the STI. The method herein negates a need to recess at least one of the fin, the first STI portion or the second STI portion during device formation. Negating a need to recess at least one of the fin, the first STI portion or the second STI portion enhances the semiconductor device formation and is more efficient than a semiconductor device formation that requires the recessing of at least one of a fin, a first STI portion or a second STI portion.