Abstract: A semiconductor device includes a substrate, a gate structure, a plurality of nanowires, a sacrificial material, and an epitaxy structure. The gate structure is disposed on and in contact with the substrate. The nanowires extend through the gate structure. The sacrificial material is separated from the gate structure. The epitaxy structure is in contact with the nanowires, is separated from the substrate, and surrounds the sacrificial material.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device includes a substrate having a fin. A first nanowire is disposed on the fin and a second nanowire is disposed on the fin, the second nanowire being laterally separated from the first nanowire. A gate structure extends around the first nanowire and the second nanowire. The gate structure also extends over a top surface of the fin. The first nanowire, the second nanowire, and the fin form a channel of a transistor.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device includes a substrate having a fin. A first nanowire is disposed on the fin and a second nanowire is disposed on the fin, the second nanowire being laterally separated from the first nanowire. A gate structure extends around the first nanowire and the second nanowire. The gate structure also extends over a top surface of the fin. The first nanowire, the second nanowire, and the fin form a channel of a transistor.

Abstract: The present disclosure describes a method which can selectively etch silicon from silicon/silicon-germanium stacks or silicon-germanium from silicon-germanium/germanium stacks to form germanium-rich channel nanowires. For example, a method can include a multilayer stack formed with alternating layers of a silicon-rich material and a germanium-rich material. A first thin chalcogenide layer is concurrently formed on the silicon-rich material, and a second thick chalcogenide layer is formed on the germanium-rich material. The first chalcogenide layer and the second chalcogenide layer are etched until the first chalcogenide layer is removed from the silicon-rich material. The silicon-rich material and the second chalcogenide layer are etched with different etch rates.

Abstract: The present disclosure describes a method which can selectively etch silicon from silicon/silicon-germanium stacks or silicon-germanium from silicon-germanium/germanium stacks to form germanium-rich channel nanowires. For example, a method can include a multilayer stack formed with alternating layers of a silicon-rich material and a germanium-rich material. A first thin chalcogenide layer is concurrently formed on the silicon-rich material, and a second thick chalcogenide layer is formed on the germanium-rich material. The first chalcogenide layer and the second chalcogenide layer are etched until the first chalcogenide layer is removed from the silicon-rich material. The silicon-rich material and the second chalcogenide layer are etched with different etch rates.

Abstract: A semiconductor device and methods of formation are provided. The semiconductor device includes a first active region having a first active region height and an active channel region having an active channel region height over a fin. The first active region height is greater than the active channel region height. The active channel region having the active channel region height has increased strain, such as increased tensile strain, as compared to an active channel region that has a height greater than the active channel region height. The increased strain increases or enhances at least one of hole mobility or electron mobility in at least one of the first active region or the active channel region. The active channel region having the active channel region height has decreased source drain leakage, as compared to an active channel region that has a height greater than the active channel region height.

Abstract: A gate-all-around field effect transistor (GAA FET) includes an InAs nano-wire as a channel layer, a gate dielectric layer wrapping the InAs nano-wire, and a gate electrode metal layer formed on the gate dielectric layer. The InAs nano-wire has first to fourth major surfaces three convex-rounded corner surfaces and one concave-rounded corner surface.

Abstract: Semiconductor device includes first and second nanowire structures disposed on semiconductor substrate extending in first direction on substrate. First nanowire structure includes plurality of first nanowires including first nanowire material extending along first direction and arranged in second direction, second direction substantially perpendicular to first direction. Second nanowire structure includes plurality of second nanowires including second nanowire material extending along first direction arranged in second direction. Second nanowire material is not same as first nanowire material. Each nanowire is spaced-apart from immediately adjacent nanowire. First and second gate structures wrap around first and second nanowires at first region of respective first and second nanowire structures. First and second gate structures include gate electrodes.

Abstract: A nanowire comprises a source region, a drain region and a channel region. The source region is modified to reduce the lifetime of minority carriers within the source region. In an embodiment the modification may be performed by implanting either amorphizing dopants or lifetime reducing dopants. Alternatively, the source may be epitaxially grown with a different materials or process conditions to reduce the lifetime of minority carriers within the source region.

Abstract: In a method of forming a Group III-V semiconductor layer on a Si substrate, a first source gas containing a Group V element is supplied to a surface of the Si substrate while heating the substrate at a first temperature, thereby terminating the Si surface with the Group V element. Then, a second source gas containing a Group III element is supplied to the surface while heating the substrate at a second temperature, thereby forming a nucleation layer directly on the surface of the Si substrate. After the nucleation layer is formed, the supply of the second source gas is stopped and the substrate is annealed at a third temperature while the first source gas being supplied, thereby foaming a seed layer. After the annealing, the second source gas is supplied while heating the substrate at a fourth temperature, thereby forming a body III-V layer semiconductor on the seed layer.

Abstract: In a method of forming a Group III-V semiconductor layer on a Si substrate, a first source gas containing a Group V element is supplied to a surface of the Si substrate while heating the substrate at a first temperature, thereby terminating the Si surface with the Group V element. Then, a second source gas containing a Group III element is supplied to the surface while heating the substrate at a second temperature, thereby forming a nucleation layer directly on the surface of the Si substrate. After the nucleation layer is formed, the supply of the second source gas is stopped and the substrate is annealed at a third temperature while the first source gas being supplied, thereby forming a seed layer. After the annealing, the second source gas is supplied while heating the substrate at a fourth temperature, thereby forming a body III-V layer semiconductor on the seed layer.

Abstract: A nanowire comprises a source region, a drain region and a channel region. The source region is modified to reduce the lifetime of minority carriers within the source region. In an embodiment the modification may be performed by implanting either amorphizing dopants or lifetime reducing dopants. Alternatively, the source may be epitaxially grown with a different materials or process conditions to reduce the lifetime of minority carriers within the source region.

Abstract: Various strained channel transistors are disclosed herein. An exemplary semiconductor device includes a substrate and a fin structure disposed over the substrate. The fin structure includes a first epitaxial layer disposed on the substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The second epitaxial layer includes a relaxed transversal stress component and a longitudinal compressive stress component, and the third epitaxial layer has uni-axial strain. A gate structure is disposed on a channel region of the fin structure, such that the gate structure interposes a source region and a drain region of the fin structure.

Abstract: A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.

Abstract: Various methods for fabricating non-planar integrated circuit devices, such as FinFET devices, are disclosed herein. An exemplary method includes forming a rib structure extending from a substrate; forming a two-dimensional material layer (including, for example, transition metal dichalcogenide or graphene) on the rib structure and the substrate; patterning the two-dimensional material layer, such that the two-dimensional material layer is disposed on at least one surface of the rib structure; and forming a gate on the two-dimensional material layer. In some implementations, a channel region, a source region, and a drain region are defined in the two-dimensional material layer. The channel region is disposed between the source region and the drain region, where the gate is disposed over the channel region. In some implementations, the patterning includes removing the two-dimensional material layer disposed on a top surface of the substrate and/or disposed on a top surface of the rib structure.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (STI) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate. The first semiconductor material has a first lattice constant and the second semiconductor material has a second lattice constant different from the first lattice constant. The fin-like active region further includes fluorine species.

Abstract: A semiconductor device and methods of formation are provided. The semiconductor device includes a gate over a channel portion of a fin. The fin includes a first active area of the fin having a first active area top surface coplanar with a first shallow trench isolation (STI) top surface of a first STI portion of STI, and a second active area of the fin having a second active area top surface coplanar with a second STI top surface of a second STI portion of the STI. The method herein negates a need to recess at least one of the fin, the first STI portion or the second STI portion during device formation. Negating a need to recess at least one of the fin, the first STI portion or the second STI portion enhances the semiconductor device formation and is more efficient than a semiconductor device formation that requires the recessing of at least one of a fin, a first STI portion or a second STI portion.

Abstract: Semiconductor devices and methods of forming the same are provided. A template layer is formed on a substrate, the template layer having a recess therein. A plurality of nanowires is formed in the recess. A gate stack is formed over the substrate, the gate stack surrounding the plurality of nanowires.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device includes a substrate having a fin. A first nanowire is disposed on the fin and a second nanowire is disposed on the fin, the second nanowire being laterally separated from the first nanowire. A gate structure extends around the first nanowire and the second nanowire. The gate structure also extends over a top surface of the fin. The first nanowire, the second nanowire, and the fin form a channel of a transistor.

Abstract: The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.