Patents by Inventor Mark Webster

Mark Webster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9274275
    Abstract: A SOI device may include a waveguide adapter that couples light between an external light source—e.g., a fiber optic cable or laser—and a silicon waveguide on the silicon surface layer of the SOI device. In one embodiment, the waveguide adapter is embedded into the insulator layer. Doing so may enable the waveguide adapter to be formed before the surface layer components are added onto the SOI device. Accordingly, fabrication techniques that use high-temperatures may be used without harming other components in the SOI device—e.g., the waveguide adapter is formed before heat-sensitive components are added to the silicon surface layer.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: March 1, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Mark Webster, Ravi Sekhar Tummidi
  • Publication number: 20160013868
    Abstract: An optical demultiplexer that includes at least one a hybrid phase shifter configured to receive a light signal over a fiber element, the light signal including polarized optical signals. Each phase shifter includes a thermo-optic phase shifter configured to phase shift the light signal, an electro-optic phase shifter configured to phase shift the light signal, and a coupler configured to maintain polarization of the polarized signal components. The optical demultiplexer also includes control circuitry configured to regulate the thermo-optic and electro-optic phase shifters.
    Type: Application
    Filed: July 8, 2014
    Publication date: January 14, 2016
    Inventors: Sean Anderson, Mark Webster, Kalpendu Shastri
  • Patent number: 9209509
    Abstract: A configuration for routing electrical signals between a conventional electronic integrated circuit (IC) and an opto-electronic subassembly is formed as an array of signal paths carrying oppositely-signed signals on adjacent paths to lower the inductance associated with the connection between the IC and the opto-electronic subassembly. The array of signal paths can take the form of an array of wirebonds between the IC and the subassembly, an array of conductive traces formed on the opto-electronic subassembly, or both.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: December 8, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Kalpendu Shastri, Bipin Dama, Mark Webster, David Piede
  • Publication number: 20150217945
    Abstract: A moving floor system that includes a moving work surface to move work products from an upstream end to a downstream end. The moving work surface is formed from a plurality of individual carts joined to each other. The stack of carts is moved along upper support rails located at an upper level. When each individual cart reaches the downstream end, a downstream lift conveyor moves the individual cart from the upper level to a lower level. When at the lower level, each individual cart is returned from the downstream end to the upstream end. When each individual cart reaches the upstream end, an upstream lift conveyor returns the individual carts from the lower level to the upper level. An upper drive mechanism provides the motive force to move the stack of carts along the upper level at the working speed.
    Type: Application
    Filed: January 27, 2015
    Publication date: August 6, 2015
    Inventors: Mark Webster, David Konopacki, Michael Reilly
  • Publication number: 20150222391
    Abstract: System (100) and methods (3500) for receive processing of a burst communication system where co-channel signals (318) collide in a receiver (150). The methods comprise: simultaneously receiving co-channel signals (2002, 2004, 2006) transmitted from remote transmitters (104-112) at a first frequency; and independently performing a first iteration of a Turbo MUD process for a first co-channel signal and a second co-channel signal. The Turbo MUD process comprises: segmenting each of the first and second co-channel signals into a plurality of segments (2102, 2104, 2106) each having a unique SINR; computing a noise plus interference variance estimate for each segment; computing first bit likelihood values for each segment based on the noise variance estimate; computing second bit likelihood values for each segment based on the first bit likelihood values; and using the second bit likelihood values (i.e., soft in soft-out) to generate a first estimate of the first and second co-channel signals.
    Type: Application
    Filed: January 31, 2014
    Publication date: August 6, 2015
    Applicant: Harris Corporation
    Inventors: MARK WEBSTER, R. Keith McPherson, Terry Tabor
  • Publication number: 20150104130
    Abstract: Embodiments of the present disclosure include devices that split a light beam into two separate paths, with reduced sensitivity to fabrication variation. The devices can operate as 3-dB splitters that divide the input optical energy equally between two output waveguides. Similarly, the devices can also function to combine two light beams into a single path (coupler). The designs make use of adiabatic modal evolution and do not require physical symmetry along the entire device length.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 16, 2015
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Sean Anderson, Ravi Sekhar Tummidi, Mark Webster
  • Publication number: 20150023630
    Abstract: An optical waveguide structure includes a rotator having a dual-layer core. A first layer of the dual-layer core may include a tapering portion. A second layer of the dual-layer core may include a rib portion disposed on the tapering portion. The combination of the rib portion and the tapering portion may receive a pair of optical signals, one being polarized in a TE mode and the other being polarized in a TM mode, and convert them to a pair of TE mode optical signals.
    Type: Application
    Filed: September 25, 2014
    Publication date: January 22, 2015
    Inventors: Sean P. Anderson, Mark A. Webster
  • Publication number: 20150010266
    Abstract: A SOI device may include a waveguide adapter that couples light between an external light source—e.g., a fiber optic cable or laser—and a silicon waveguide on the silicon surface layer of the SOI device. In one embodiment, the waveguide adapter is embedded into the insulator layer. Doing so may enable the waveguide adapter to be formed before the surface layer components are added onto the SOI device. Accordingly, fabrication techniques that use high-temperatures may be used without harming other components in the SOI device—e.g., the waveguide adapter is formed before heat-sensitive components are added to the silicon surface layer.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 8, 2015
    Applicant: Cisco Technology, Inc.
    Inventors: Mark Webster, Ravi Sekhar Tummidi
  • Publication number: 20140362457
    Abstract: An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.
    Type: Application
    Filed: July 15, 2014
    Publication date: December 11, 2014
    Inventors: Mary NADEAU, Vipulkumar PATEL, Prakash GOTHOSKAR, John FANGMAN, John Matthew FANGMAN, Mark WEBSTER
  • Patent number: 8873899
    Abstract: An optical waveguide structure includes a rotator having a dual-layer core. A first layer of the dual-layer core may include a tapering portion. A second layer of the dual-layer core may include a rib portion disposed on the tapering portion. The combination of the rib portion and the tapering portion may receive a pair of optical signals, one being polarized in a TE mode and the other being polarized in a TM mode, and convert them to a pair of TE mode optical signals.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 28, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Sean P. Anderson, Mark A. Webster
  • Publication number: 20140294334
    Abstract: A configuration for routing electrical signals between a conventional electronic integrated circuit (IC) and an opto-electronic subassembly is formed as an array of signal paths carrying oppositely-signed signals on adjacent paths to lower the inductance associated with the connection between the IC and the opto-electronic subassembly. The array of signal paths can take the form of an array of wirebonds between the IC and the subassembly, an array of conductive traces formed on the opto-electronic subassembly, or both.
    Type: Application
    Filed: March 18, 2014
    Publication date: October 2, 2014
    Applicant: Cisco Technology, Inc.
    Inventors: Kalpendu SHASTRI, Bipin DAMA, Mark WEBSTER, David PIEDE
  • Patent number: 8848812
    Abstract: A mixed waveform configuration for wireless communications including a first portion that is modulated according to a single-carrier modulation scheme and a second portion that is modulated according to a multi-carrier modulation scheme. The waveform is specified so that a channel impulse response (CIR) estimate obtainable from the first portion is reusable for acquisition of the second portion. The first portion includes a preamble and header and the second portion typically incorporates the payload.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: September 30, 2014
    Assignee: Intellectual Ventures I LLC
    Inventors: Mark A Webster, Michael J Seals
  • Publication number: 20140270620
    Abstract: An optical waveguide structure includes a rotator having a dual-layer core. A first layer of the dual-layer core may include a tapering portion. A second layer of the dual-layer core may include a rib portion disposed on the tapering portion. The combination of the rib portion and the tapering portion may receive a pair of optical signals, one being polarized in a TE mode and the other being polarized in a TM mode, and convert them to a pair of TE mode optical signals.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: Cisco Technology, Inc.
    Inventors: Sean P. Anderson, Mark A. Webster
  • Patent number: 8836100
    Abstract: An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: September 16, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Mary Nadeau, Vipulkumar Patel, Prakash Gothoskar, John Fangman, John Matthew Fangman, Mark Webster
  • Publication number: 20140248723
    Abstract: A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.
    Type: Application
    Filed: May 13, 2014
    Publication date: September 4, 2014
    Applicant: Cisco Technology, Inc.
    Inventors: Kalpendu SHASTRI, Vipulkumar PATEL, Mark WEBSTER, Prakash GOTHOSKAR, Ravinder KACHRU, Soham PATHAK, Rao V. YELAMARTY, Thomas DAUGHERTY, Bipin DAMA, Kaushik PATEL, Kishor DESAI
  • Patent number: 8803269
    Abstract: A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: August 12, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Kalpendu Shastri, Vipulkumar Patel, Mark Webster, Prakash Gothoskar, Ravinder Kachru, Soham Pathak, Rao V. Yelamarty, Thomas Daugherty, Bipin Dama, Kaushik Patel, Kishor Desai
  • Patent number: 8724939
    Abstract: A configuration for routing electrical signals between a conventional electronic integrated circuit (IC) and an opto-electronic subassembly is formed as an array of signal paths carrying oppositely-signed signals on adjacent paths to lower the inductance associated with the connection between the IC and the opto-electronic subassembly. The array of signal paths can take the form of an array of wirebonds between the IC and the subassembly, an array of conductive traces formed on the opto-electronic subassembly, or both.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: May 13, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Kalpendu Shastri, Bipin Dama, Mark Webster, David Piede
  • Patent number: 8705335
    Abstract: Various packet processing systems and methods are disclosed. One method embodiment, among others, comprises providing a legacy long training symbol (LTS), and inserting subcarriers in the legacy LTS to form an extended LTS (ELTS).
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: April 22, 2014
    Assignee: Intellectual Ventures I LLC
    Inventors: Mark A Webster, Michael J Seals
  • Patent number: 8618625
    Abstract: A planar, waveguide-based silicon Schottky barrier photodetector includes a third terminal in the form of a field plate to improve the responsivity of the detector. Preferably, a silicide used for the detection region is formed during a processing step where other silicide contact regions are being formed. The field plate is preferably formed as part of the first or second layer of CMOS metallization and is controlled by an applied voltage to modify the electric field in the vicinity of the detector's silicide layer. By modifying the electric field, the responsivity of the device is “tuned” so as to adjust the momentum of “hot” carriers (electrons or holes, depending on the conductivity of the silicon) with respect to the Schottky barrier of the device.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: December 31, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Vipulkumar Patel, Prakash Gothoskar, Mark Webster, Christopher J. Lang
  • Patent number: 8620115
    Abstract: A semiconductor-based optical modulator is presented that includes a separate phase control section to adjust the amount of chirp present in the modulated output signal. At least one section is added to the modulator configuration and driven to create a pure “phase” signal that will is added to the output signal and modify the ei? term inherent in the modulation function. The phase modulation control section may be located within the modulator itself, or may be disposed “outside” of the modulator on either the input waveguiding section or the output waveguiding section. The phase control section may be formed to comprise multiple segments (of different lengths), with the overall phase added to the propagating signal controlled by selecting the different segments to be energized to impart a phase delay to a signal propagating through the energized section(s).
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: December 31, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Mark Webster, Kalpendu Shastri