Abstract: A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwanted portion of an initially deposited contact layer. Moreover, due to the inventive concept, the strain-inducing contact layers may be formed directly on the respective substantially L-shaped spacer elements, thereby enhancing even more the stress transfer mechanism.

Abstract: A substrate comprising a first transistor element and a second transistor element is provided. A layer of a material is deposited over the first transistor element and the second transistor element. A portion of the layer of material is modified, which may be done, e.g., by irradiating the portion with ions or performing an isotropic etching process to reduce its thickness. An etching process adapted to remove the modified portion of the layer of material more quickly than an unmodified portion of the layer located over the second transistor element is performed.

Abstract: By performing an anisotropic resist modification prior to the actual resist trimming process, the profile of the end portions of the resist features may be significantly enhanced, for instance by providing substantially vertical sidewall portions. Consequently, an overlap of gate electrodes with the respective isolation structures may be obtained, while nevertheless the probability for a short circuit between opposing end portions of the gate electrodes may be significantly reduced, thereby providing the potential for further scaling down device dimensions.

Abstract: By forming a stressed semiconductor material in a gate electrode, a biaxial tensile strain may be induced in the channel region, thereby significantly increasing the charge carrier mobility. This concept may be advantageously combined with additional strain-inducing sources, such as embedded strained semiconductor materials in the drain and source regions, thereby providing the potential for enhancing transistor performance without contributing to process complexity.

Abstract: By consuming a surface portion of polysilicon material or silicon material after implantation and prior to activation of dopants, contaminants may be efficiently removed, thereby significantly enhancing the process uniformity during a subsequent silicidation process. Hence, the defect rate during the silicidation process, for instance “missing silicide” defects, may be significantly reduced, thereby also enhancing the reliability of static RAM cells.

Abstract: A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwanted portion of an initially deposited contact layer. Moreover, due to the inventive concept, the strain-inducing contact layers may be formed directly on the respective substantially L-shaped spacer elements, thereby enhancing even more the stress transfer mechanism.

Abstract: By providing an asymmetric design of a halo region and extension regions of a field effect transistor, the transistor performance may significantly be enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even completely be avoided, wherein a moderately reduced concentration gradient may further enhance the transistor performance.

Abstract: By removing an outer spacer, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer may be positioned more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region.

Abstract: The present invention provides a technique that enables the formation of a recessed spacer element by using an anisotropically deposited etch stop layer. Accordingly, in subsequent cleaning processes, material residues of the etch stop layer may be efficiently removed from upper sidewall portions of a line element, thereby increasing the available area for a diffusion path in a subsequent silicidation process. The anisotropic deposition of the etch stop layer may be accomplished by high density plasma enhanced CVD or by directional sputter techniques.

Abstract: A substrate comprising a first transistor element and a second transistor element is provided. A layer of a material is deposited over the first transistor element and the second transistor element. A portion of the layer of material is modified, which may be done, e.g., by irradiating the portion with ions or performing an isotropic etching process to reduce its thickness. An etching process adapted to remove the modified portion of the layer of material more quickly than an unmodified portion of the layer located over the second transistor element is performed.

Abstract: By providing an asymmetric design of a halo region and extension regions of a field effect transistor, the transistor performance may significantly be enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even completely be avoided, wherein a moderately reduced concentration gradient may further enhance the transistor performance.

Abstract: The present invention allows the formation of sidewall spacers adjacent a feature on a substrate without there being an undesirable erosion of the feature. The feature is covered by one or more protective layers. A layer of a spacer material is deposited over the feature and etched anisotropically. An etchant used in the anisotropic etching is adapted to selectively remove the spacer material, whereas the one or more protective layers are substantially not affected by the etchant. Thus, the one or more protective layers protect the feature from being exposed to the etchant.

Abstract: The present invention provides a technique that enables the formation of a recessed spacer element by using an anisotropically deposited etch stop layer. Accordingly, in subsequent cleaning processes, material residues of the etch stop layer may be efficiently removed from upper sidewall portions of a line element, thereby increasing the available area for a diffusion path in a subsequent silicidation process. The anisotropic deposition of the etch stop layer may be accomplished by high density plasma enhanced CVD or by directional sputter techniques.

Abstract: By reducing a deposition rate and maintaining a low bias power in a plasma atmosphere, a spacer layer, for example a silicon nitride layer, may be deposited that exhibits tensile stress. The amount of tensile stress is controllable within a wide range, thereby providing the potential for forming sidewall spacer elements that modify the charge carrier mobility and thus the conductivity of the channel region of a field effect transistor.

Abstract: In highly sophisticated MOS transistors including nickel silicide portions for reducing the silicon sheet resistance, nickel silicide stingers may lead to short circuits between the drain and source region and the channel region, thereby significantly lowering production yield. By substantially amorphizing corresponding portions of the source and drain regions, the creation of clustered point defects may effectively be avoided during curing implantation induced damage, wherein a main diffusion path for nickel during the nickel silicide formation is interrupted. Thus, nickel silicide stingers may be significantly reduced or even completely avoided.