Patents by Inventor Markus Zundel

Markus Zundel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10707342
    Abstract: Disclosed is a transistor device and a method for producing thereof. The transistor device includes at least one transistor cell, wherein the at least one transistor cell includes: a source region, a body region and a drift region in a semiconductor body; a gate electrode dielectrically insulated from the body region by a gate dielectric; a field electrode dielectrically insulated from the drift region by a field electrode dielectric; and a contact plug extending from a first surface of the semiconductor body to the field electrode and adjoining the source region and the body region.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: July 7, 2020
    Assignee: Infineon Technology Austria AG
    Inventors: Markus Zundel, Franz Hirler
  • Patent number: 10672661
    Abstract: A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Christian Westermeier, Jochen Hilsenbeck, Jens Peter Konrath, Boris Mayerhofer, Anatoly Sotnikov
  • Publication number: 20200152621
    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, and a pn junction diode electrically connected in series with the resistor.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
  • Publication number: 20200135564
    Abstract: A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Christian Westermeier, Jochen Hilsenbeck, Jens Peter Konrath, Boris Mayerhofer, Anatoly Sotnikov
  • Publication number: 20200091284
    Abstract: A semiconductor device includes a semiconductor body having a first surface. A first trench extends in a vertical direction into the semiconductor body. The semiconductor device also includes a first interlayer in the first trench and a first dopant source in the first trench. The first interlayer is arranged between the first dopant source and the semiconductor body, and the first dopant source includes a first dopant species. The semiconductor device also includes a semiconductor area doped with the first dopant species and which completely surrounds the first trench at least at a depth in the semiconductor body and adjoins the first trench.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 19, 2020
    Inventor: Markus Zundel
  • Patent number: 10593799
    Abstract: A semiconductor component includes a field-effect transistor arrangement having a drift zone and body region between the drift zone and a first surface of a semiconductor body. Trench structures of a first type extend from the first surface into the semiconductor body and have a maximum lateral dimension at the first surface which is less than a depth of first and second ones of the trench structures. A net doping concentration at a reference depth at a first location in the drift zone is at least 10% greater than at a second location in the drift zone at the reference depth, which is located between the body region and a bottom of the first trench structure. The first location is at the same first lateral distance from the first and second trench structures. The second location is at the same second lateral distance from the first and second trench structures.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: March 17, 2020
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Karl-Heinz Bach, Peter Brandl, Andrew Christopher Graeme Wood
  • Patent number: 10586792
    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: March 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
  • Publication number: 20190334000
    Abstract: A transistor component includes at least one transistor cell having: a drift region, a source region, a body region and a drain region in a semiconductor body, the body region being arranged between the source and drift regions, and the drift region being arranged between the body and drain regions; a gate electrode arranged adjacent to the body region and dielectrically isolated from the body region by a gate dielectric; and a field electrode arranged adjacent to the drift region and dielectrically isolated from the drift region by a field electrode dielectric. The field electrode dielectric has a thickness that increases in a direction toward the drain region. The drift region has, in a mesa region adjacent to the field electrode, a doping concentration that increases in the direction toward the drain region.
    Type: Application
    Filed: April 24, 2019
    Publication date: October 31, 2019
    Inventors: Markus Zundel, Karl-Heinz Bach, Peter Brandl, Franz Hirler, Andrew Christopher Graeme Wood
  • Patent number: 10453915
    Abstract: A semiconductor device includes a semiconductor body having a semiconductor substrate of a first conductivity type and a semiconductor layer of the first conductivity type on the substrate. A trench structure extends into the semiconductor body from a first surface and includes a gate electrode and at least one field electrode arranged between the gate electrode and a bottom side of the trench structure. A body region adjoins the trench structure and laterally extends from a transistor cell area into an edge termination area. A pn junction is between the body region and semiconductor layer. A doping concentration of at least one of the body region and semiconductor layer is lowered at a lateral end of the pn junction in the edge termination area compared to a doping concentration of the at least one of the body region and semiconductor layer at the pn junction in the transistor cell area.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: October 22, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Karl-Heinz Bach, Christian Kampen, Dietmar Kotz, Andrew Christopher Graeme Wood, Markus Zundel
  • Patent number: 10439030
    Abstract: A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: October 8, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Rolf Weis, Franz Hirler, Martin Vielemeyer, Markus Zundel, Peter Irsigler
  • Patent number: 10403556
    Abstract: A semiconductor device includes a drift structure formed in a semiconductor body. The drift structure forms a first pn junction with a body zone of a transistor cell. A gate structure extends from a first surface of the semiconductor body into the drift structure. A heat sink structure extends from the first surface into the drift structure. A thermal conductivity of the heat sink structure is greater than a thermal conductivity of the gate structure and/or a thermal capacity of the heat sink structure is greater than a thermal capacity of the gate structure.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Peter Irsigler, Joachim Mahler, Guenther Ruhl, Hans-Joachim Schulze, Markus Zundel
  • Patent number: 10340227
    Abstract: In various embodiments, a die is provided. The die may include a die body, and at least one of a front side metallization structure on a front side of the die body and a back side metallization structure on a back side of the die body such that the die is plane or includes a positive radius of curvature at a die attach process temperature range.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 2, 2019
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Manfred Schneegans
  • Publication number: 20190198661
    Abstract: Disclosed is a transistor device and a method for producing thereof. The transistor device includes at least one transistor cell, wherein the at least one transistor cell includes: a source region, a body region and a drift region in a semiconductor body; a gate electrode dielectrically insulated from the body region by a gate dielectric; a field electrode dielectrically insulated from the drift region by a field electrode dielectric; and a contact plug extending from a first surface of the semiconductor body to the field electrode and adjoining the source region and the body region.
    Type: Application
    Filed: March 1, 2019
    Publication date: June 27, 2019
    Inventors: Markus Zundel, Franz Hirler
  • Publication number: 20190157259
    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.
    Type: Application
    Filed: December 31, 2018
    Publication date: May 23, 2019
    Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
  • Publication number: 20190157449
    Abstract: A semiconductor device includes a semiconductor body includes a first side and a second side opposite to the first side, a first dielectric disposed on the first side, a second dielectric disposed on the second side, one or more FET devices disposed at the first side, a first contact trench extending through the first dielectric at the first side, a first conductive material disposed in the first contact trench and electrically connected to the semiconductor body, a second contact trench extending through the second dielectric and into the semiconductor body at the second side, and a second conductive material disposed in the second contact trench and electrically connected to the semiconductor body at sidewalls of the second contact trench.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 23, 2019
    Inventors: Markus Zundel, Andreas Meiser, Hans-Peter Lang, Thorsten Meyer, Peter Irsigler
  • Patent number: 10276706
    Abstract: A gated diode in a press-fit housing includes a base configured to be press-fit into an opening of a diode carrier plate and including a pedestal portion with a first flat surface, and a head wire including a head portion with a second flat surface and a wire portion. The base and the head wire form parts of the press-fit housing. The gated diode in the press-fit housing further includes a semiconductor die, a first solder layer engaging and electrically connecting the semiconductor die with the first flat surface of the base, and a second solder layer engaging and electrically connecting the semiconductor die with the second flat surface of the head wire.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: April 30, 2019
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Markus Zundel, Dietrich Bonart, Ludger Borucki
  • Publication number: 20190109226
    Abstract: An alternator assembly includes an input terminal configured to input an alternating voltage, an output terminal configured to output a rectified voltage, and a gated diode arranged in a load path between the input terminal and the output terminal.
    Type: Application
    Filed: November 27, 2018
    Publication date: April 11, 2019
    Inventors: Dirk Ahlers, Markus Zundel, Dietrich Bonart, Ludger Borucki
  • Patent number: 10243071
    Abstract: Disclosed is a transistor device and a method for producing thereof. The transistor device includes at least one transistor cell, wherein the at least one transistor cell includes: a source region, a body region and a drift region in a semiconductor body; a gate electrode dielectrically insulated from the body region by a gate dielectric; a field electrode dielectrically insulated from the drift region by a field electrode dielectric; and a contact plug extending from a first surface of the semiconductor body to the field electrode and adjoining the source region and the body region.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 26, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Zundel, Franz Hirler
  • Patent number: 10217830
    Abstract: A semiconductor device includes a plurality of trenches extending into a semiconductor substrate. Each trench comprises a plurality of enlarged width regions distributed along the trench. At least one electrically conductive trench structure is located in each trench. The semiconductor device comprises an electrically insulating layer arranged between the semiconductor substrate and an electrode structure. The semiconductor device comprises a vertical electrically conductive structure extending through the electrically insulating layer. The vertical electrically conductive structure forms an electrically connection between the electrode structure and an electrically conductive trench structure located in a first trench of at a first enlarged width region.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Thomas Ostermann, Michael Sorger
  • Patent number: RE47710
    Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: November 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Zundel, Franz Hirler, Armin Willmeroth