Abstract: A semiconductor workpiece includes a semiconductor substrate, at least two chip areas, components of semiconductor devices being formed in the semiconductor substrate in the at least two chip areas, and a separation trench disposed between adjacent chip areas. The separation trench is formed in a first main surface of the semiconductor substrate and extends from the first main surface to a second main surface of the semiconductor substrate. The second main surface is disposed opposite to the first main surface. The separation trench is filled with at least one sacrificial material.

Abstract: In various embodiments, a die is provided. The die may include a die body, and at least one of a front side metallization structure on a front side of the die body and a back side metallization structure on a back side of the die body such that the die is plane or includes a positive radius of curvature at a die attach process temperature range.

Abstract: What is provided is a field effect component including a semiconductor body, which extends in an edge zone from a rear side as far as a top side and which includes a semiconductor mesa, which extends in a vertical direction, which is perpendicular to the rear side and/or the top side. The semiconductor body in a vertical cross section further includes a drift region, which extends at least in the edge region as far as the top side and which is arranged partly in the semiconductor mesa, and a body region, which is arranged at least partly in the semiconductor mesa and which forms a pn junction with the drift region. The pn junction extends between two sidewalls of the semiconductor mesa.

Abstract: A controllable semiconductor component is produced by providing a semiconductor body with a top side and a bottom side, and forming a first trench protruding from the top side into the semiconductor body and a second trench protruding from the top side into the semiconductor body. In a common process, an oxide layer is formed in the first trench and in the second trench such that the oxide layer fills the first trench and electrically insulates a surface of the second trench. The oxide layer is removed from the first trench completely or at least partly such that the semiconductor body has an exposed first surface area arranged in the first trench. An electrically conductive material is filled into the second trench, and the semiconductor body and the oxide layer are partially removed such that the electrically conductive material has an exposed second surface area at the bottom side.

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: providing a semiconductor device having a first pad and a second pad electrically disconnected from the first pad; applying at least one electrical test potential to at least one of the first pad and the second pad; and electrically connecting the first pad and the second pad to one another after applying the at least one electrical test potential.

Abstract: A semiconductor device is formed by forming: a transistor in a semiconductor substrate having a main surface; a source region and a drain region; and a channel region and a drift zone between the source region and the drain region. The source and drain regions are arranged along a first direction parallel to the main surface. Gate trenches and a gate electrode are formed in the gate trenches. The gate trenches have a distance corresponding to a width d1 of the channel region, where d1?2*ld and ld denotes a length of a depletion zone formed at an interface between the channel region and a gate dielectric adjacent to the gate electrode. An auxiliary trench formed in the main surface extends in a second direction intersecting the first direction. The source region is formed using a doping method that introduces dopants via a sidewall of the auxiliary trench.

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate of a first conductivity type having a continuous first area and a second area, introducing dopants of the first conductivity type in the continuous first area of the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer, and forming trenches in the second semiconductor layer in the continuous first area.

Abstract: A device includes a semiconductor chip. An outline of a frontside of the semiconductor chip includes at least one of a polygonal line including two line segments joined together at an inner angle of greater than 90° and an arc-shaped line.

Abstract: A semiconductor component includes a semiconductor body having a bottom side, a top side spaced distant from the bottom side in a vertical direction, and a thickness in the vertical direction, and a crack sensor configured to detect a crack in the semiconductor body. The crack sensor extends into the semiconductor body. A distance between the crack sensor and the bottom side is less than the thickness of the semiconductor body. A crack in the semiconductor body is detected by specifying a first value of a characteristic variable of the crack sensor, determining a second value of the characteristic variable of the crack sensor at a different time than the first value is specified, and determining the semiconductor body has a crack if the second value differs from the first value by more than a pre-defined difference.

Abstract: A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.

Abstract: A power semiconductor package includes a housing, a semiconductor chip embedded in the housing, and at least four terminals partially embedded in the housing and partially exposed to the outside of the housing. The semiconductor chip includes a first doping region in ohmic contact with a first metal layer, a second doping region in ohmic contact with a second metal layer, and a plurality of first trenches that includes gate electrodes and first field electrodes electrically insulated from the gate electrodes. A first terminal of the four terminals is electrically connected to the first metal layer, a second terminal of the four terminals is electrically connected to the second metal layer, a third terminal of the four terminals is electrically connected to the gate electrodes of the first trenches, and a fourth terminal of the four terminals is electrically connected to the first field electrodes of the first trenches.

Abstract: A gated diode in a press-fit housing includes a base configured to be press-fit into an opening of a diode carrier plate and including a pedestal portion with a first flat surface, and a head wire including a head portion with a second flat surface and a wire portion. The base and the head wire form parts of the press-fit housing. The gated diode in the press-fit housing further includes a semiconductor die, a first solder layer engaging and electrically connecting the semiconductor die with the first flat surface of the base, and a second solder layer engaging and electrically connecting the semiconductor die with the second flat surface of the head wire.

Abstract: A field-effect semiconductor device is provided. The field-effect semiconductor device includes a semiconductor body with a first surface defining a vertical direction. In a vertical cross-section the field-effect semiconductor device further includes a vertical trench extending from the first surface into the semiconductor body and comprising a field electrode, a cavity at least partly surrounded by the field electrode, and an insulation structure substantially surrounding at least the field electrode. An interface between the insulation structure and the surrounding semiconductor body is under tensile stress and the cavity is filled or unfilled so as to counteract the tensile stress.

Abstract: A semiconductor device in a semiconductor substrate includes a trench in a first main surface of the semiconductor substrate. The trench includes a first trench portion extending in a first direction and a second trench portion extending in the first direction. The first trench portion is connected with the second trench portion in a lateral direction. The first trench portion and the second trench portion are arranged one after the other along the first direction. The semiconductor device further includes a trench conductive structure having a conductive material disposed in the first trench portion, and a trench capacitor structure having a capacitor dielectric and a first capacitor electrode disposed in the second trench portion. The first capacitor electrode includes a layer lining a sidewall of the second trench portion.

Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.

Abstract: What is provided is a field effect component including a semiconductor body, which extends in an edge zone from a rear side as far as a top side and which includes a semiconductor mesa, which extends in a vertical direction, which is perpendicular to the rear side and/or the top side. The semiconductor body in a vertical cross section further includes a drift region, which extends at least in the edge region as far as the top side and which is arranged partly in the semiconductor mesa, and a body region, which is arranged at least partly in the semiconductor mesa and which forms a pn junction with the drift region. The pn junction extends between two sidewalls of the semiconductor mesa.

Abstract: A semiconductor device includes a semiconductor body having first and second opposing sides. Contact trenches extend, from the first and second sides, through a dielectric and into the semiconductor body. The contact trenches include conductive material electrically connected to the semiconductor body via sidewalls. The contact trenches include a first contact trench extending through a first dielectric and into the semiconductor body at the first side, the first contact trench including a first conductive material electrically connected to the semiconductor body adjoining the first contact trench, a second contact trench extending through a second dielectric and into the semiconductor body at the second side, the second contact trench including a second conductive material, a first contact pattern surrounded by the first dielectric at the first side, and a second contact pattern surrounded by the second dielectric at the second side.

Abstract: A method of manufacturing a semiconductor device includes forming a continuous silicate glass structure over a first surface of a semiconductor body, including a first part of the continuous glass structure over an active area of the semiconductor body and a second part of the continuous glass structure over an area of the semiconductor body outside of the active area. A first composition of dopants included in the first part of continuous glass structure differs from a second composition of dopants of the second part of the continuous glass structure.

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doping regions of a first doping structure arranged at a main surface of the semiconductor substrate and a plurality of second doping regions of the first doping structure arranged at the main surface of the semiconductor substrate. The first doping regions of the plurality of first doping regions of the first doping structure include dopants of a first conductivity type with different doping concentrations. Further, the second doping regions of the plurality of second doping regions of the first doping structure include dopants of a second conductivity type with different doping concentrations. At least one first doping region of the plurality of first doping regions of the first doping structure partly overlaps at least one second doping region of the plurality of second doping regions of the first doping structure causing an overlap region arranged at the main surface.

Abstract: Disclosed is a transistor device. The transistor device includes a plurality of field structures which define a plurality of semiconductor mesa regions in a semiconductor body, and each of which comprises a field electrode and a field electrode dielectric; a plurality of gate structures in each semiconductor mesa region, wherein each gate structure comprises a gate electrode and a gate dielectric, and is arranged in a trench of the semiconductor mesa region; a plurality of body regions, a plurality of source regions, and a drift region. Each body region adjoins the gate dielectric of at least one of the plurality of gate structures, and is located between one of the plurality of source regions and the drift region.