Patents by Inventor Martin Foltin

Martin Foltin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200312406
    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
  • Publication number: 20200285779
    Abstract: Examples described herein relate to a security system consistent with the disclosure. For instance, the security system may comprise a sensor interface bridge connecting a gateway to an input/output (I/O) card, a Field Programmable Gate Array (FPGA) to scan data to detect an anomaly in the data while the data is in the sensor interface bridge, where a learning neural network accelerator Application-Specific Integrated Circuit (ASIC) is integrated with the FPGA and send the data without an anomaly to the gateway.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 10, 2020
    Inventors: Martin Foltin, Aalap Tripathy, Harvey Edward White, JR., John Paul Strachan
  • Patent number: 10735030
    Abstract: A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: August 4, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Harvey Ray, Kevin L. Miller, Chris Michael Brueggen, Martin Foltin
  • Patent number: 10671291
    Abstract: Example implementations relate to memory read requests. For example, an implementation may include tracking progress of an iterative write sequence to write data to a memory element of a memory module. A received read request is detected to be addressed to a memory bank that includes the memory element undergoing the iterative write sequence. Based on the tracked progress, a time is determined to interrupt the iterative write sequence with insertion of the read request. The time aligns between operations of the iterative write sequence and data is returned within a predetermined read latency.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: June 2, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B Lesartre, Martin Foltin
  • Publication number: 20200073755
    Abstract: A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.
    Type: Application
    Filed: August 28, 2018
    Publication date: March 5, 2020
    Inventors: John Paul Strachan, Catherine Graves, Dejan S. Milojicic, Paolo Faraboschi, Martin Foltin, Sergey Serebryakov
  • Publication number: 20200066676
    Abstract: According to an example, a dual in-line memory module (DIMM) may include a high density package substrate including a plurality of connectors for communicatively interconnecting the DIMM to a system.
    Type: Application
    Filed: February 5, 2016
    Publication date: February 27, 2020
    Inventors: Gregg B. Lesartre, Jason H. Culler, Martin Foltin, William S. Jaffe
  • Publication number: 20200042287
    Abstract: Disclosed techniques provide for dynamically changing precision of a multi-stage compute process. For example, changing neural network (NN) parameters on a per-layer basis depending on properties of incoming data streams and per-layer performance of an NN among other considerations. NNs include multiple layers that may each be calculated with a different degree of accuracy and therefore, compute resource overhead (e.g., memory, processor resources, etc.). NNs are usually trained with 32-bit or 16-bit floating-point numbers. Once trained, an NN may be deployed in production. One approach to reduce compute overhead is to reduce parameter precision of NNs to 16 or 8 for deployment. The conversion to an acceptable lower precision is usually determined manually before deployment and precision levels are fixed while deployed.
    Type: Application
    Filed: August 1, 2018
    Publication date: February 6, 2020
    Inventors: Sai Rahul Chalamalasetti, Paolo Faraboschi, Martin Foltin, Catherine Graves, Dejan S. Milojicic, Sergey Serebryakov, John Paul Strachan
  • Patent number: 10490270
    Abstract: A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator concurrently applies a read voltage to the resistive memory cell and the reference cell via a memory row address. A sensing circuit enables the function generator and monitors a target current received from the resistive memory cell when selected via a memory column address and monitors a reference current received when selected via a reference column address in response to the read voltage applied to the memory row address. A current comparator circuit in the sensing circuit compares a difference between the target current and the reference current to determine the memory state of the resistive memory cell.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: November 26, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: James S Ignowski, Martin Foltin, Yoocharn Jeon
  • Patent number: 10460800
    Abstract: A data storage device includes a memory cell array and sense circuitry to detect a data value stored to a memory cell of the memory cell array. The data storage device also includes a controller to bias the sense circuitry during a read phase of a write operation to increase the probability that the sense circuitry will detect an opposite value that is opposite from the value being written to the memory cell.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: October 29, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B Lesartre, Martin Foltin, Yoocharn Jeon
  • Patent number: 10452472
    Abstract: A dot-product engine (DPE) implemented on an integrated circuit as a crossbar array (CA) includes memory elements comprising a memristor and a transistor in series. A crossbar with N rows, M columns may have N×M memory elements. A vector input for N voltage inputs to the CA and a vector output for M voltage outputs from the CA. An analog-to-digital converter (ADC) and/or a digital-to-analog converter (DAC) may be coupled to each input/output register. Values representing a first matrix may be stored in the CA. Voltages/currents representing a second matrix may be applied to the crossbar. Ohm's Law and Kirchoff's Law may be used to determine values representing the dot-product as read from the crossbar. A portion of the crossbar may perform Error-correcting Codes (ECC) concurrently with calculating the dot-product results. ECC codes may be used to only indicate detection of errors, or for both detection and correction of results.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 22, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Catherine Graves, John Paul Strachan, Dejan S. Milojicic, Paolo Faraboschi, Martin Foltin, Sergey Serebryakov
  • Patent number: 10318205
    Abstract: A method for managing data using a number of non-volatile memory arrays is described. The method includes writing data from a volatile memory region to a first non-volatile memory array. The method also includes writing a remaining portion of the data from the volatile memory region to a second non-volatile memory array in response to detecting that an event has occurred. The second non-volatile memory array has a lower write latency than the first non-volatile memory array.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: June 11, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Martin Foltin
  • Patent number: 10312943
    Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: June 4, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Craig Warner, Martin Foltin, Chris Michael Brueggen, Brian S. Birk, Harvey Ray
  • Patent number: 10275307
    Abstract: A method is provided. In an example, the method includes identifying a memory module that includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a plurality of memory regions, and each memory die of the plurality of memory dies services a respective portion of a data access. An error pattern is detected in a first memory region of the plurality of memory regions. The first memory region is associated with a first memory die of the plurality of memory dies. Based on the detected error pattern, the first memory region of the first memory die is marked as erased without marking a second memory region of the first memory die as erased.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: April 30, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Craig Warner, Martin Foltin, Chris Michael Brueggen
  • Publication number: 20190044546
    Abstract: A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.
    Type: Application
    Filed: August 7, 2017
    Publication date: February 7, 2019
    Inventors: Gregg B. Lesartre, Harvey Ray, Kevin L. Miller, Chris Michael Brueggen, Martin Foltin
  • Patent number: 10191884
    Abstract: A method for managing a multi-lane serial link is described. The method includes establishing a serial link between a number of integrated circuits across a first number of lanes. The first number of lanes are a subset of a number of available lanes on the serial link. The method also includes selecting to change a transmission state of a second number of lanes. The second number of lanes are a subset of the available lanes. The method also includes changing the transmission state of the second number of lanes while transmitting data on a number of remaining lanes. The method further includes synchronizing the first number of lanes and the second number of lanes.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: January 29, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Martin Foltin
  • Patent number: 10157668
    Abstract: An example device in accordance with an aspect of the present disclosure includes at least one current comparator, a plurality of threshold currents, and a controller. The current comparator is to compare a memristor current to a plurality of threshold currents. The controller is to set a desired memristance state of a memristor according to a memristance feedback tuning loop based on a plurality of threshold levels. The controller is to apply positive and negative voltages to the memristor during the feedback tuning loop to achieve the desired memristance state of the memristor.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: December 18, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Luke Whitaker, Emmanuelle J. Merced Grafals, Martin Foltin
  • Publication number: 20180358093
    Abstract: The present disclosure provides a data storage device that includes a memory cell array and sense circuitry to detect a data value stored to a memory cell of the memory cell array. The data storage device also includes a controller to bias the sense circuitry during a read phase of a write operation to increase the probability that the sense circuitry will detect an opposite value that, is opposite from the value being written to the memory cell.
    Type: Application
    Filed: July 31, 2015
    Publication date: December 13, 2018
    Inventors: Gregg B Lesartre B LESARTRE, Martin FOLTIN, Yoocharn JEON
  • Publication number: 20180314437
    Abstract: Example implementations relate to memory read requests. For example, an implementation may include tracking progress of an iterative write sequence to write data to a memory element of a memory module. A received read request is detected to be addressed to a memory bank that includes the memory element undergoing the iterative write sequence. Based on the tracked progress, a time is determined to interrupt the iterative write sequence with insertion of the read request. The time aligns between operations of the iterative write sequence and data is returned within a predetermined read latency.
    Type: Application
    Filed: November 17, 2015
    Publication date: November 1, 2018
    Inventors: Gregg B LESARTRE, Martin FOLTIN
  • Publication number: 20180301187
    Abstract: A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator concurrently applies a read voltage to the resistive memory cell and the reference cell via a memory row address. A sensing circuit enables the function generator and monitors a target current received from the resistive memory cell when selected via a memory column address and monitors a reference current received when selected via a reference column address in response to the read voltage applied to the memory row address. A current comparator circuit in the sensing circuit compares a difference between the target current and the reference current to determine the memory state of the resistive memory cell.
    Type: Application
    Filed: October 28, 2015
    Publication date: October 18, 2018
    Inventors: James S IGNOWSKI, Martin FOLTIN, Yoocharn JEON
  • Publication number: 20180276068
    Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.
    Type: Application
    Filed: March 24, 2017
    Publication date: September 27, 2018
    Inventors: Gregg B. Lesartre, Craig Warner, Martin Foltin, Chris Michael Brueggen, Brian S. Birk, Harvey Ray