Abstract: A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.

Abstract: A memristor memory is disclosed. In an example, a method of controlling a memristor memory includes operating the memristor memory in a volatile mode, wherein switching a state of a memristor cell is with a low writing load. The method also includes operating the same memristor memory in a non-volatile mode, wherein switching a state of the memristor cell is with a high writing load.

Abstract: An apparatus includes a first resistive storage element and a second resistive storage element. The first and second resistive storage elements are coupled to column lines to of a crosspoint array to form a memory cell; and a ratio of resistances of the first and second resistive storage elements indicates a stored value for the memory cell.

Abstract: A method for managing a multi-lane serial link is described. The method includes establishing a serial link between a number of integrated circuits across a first number of lanes. The first number of lanes are a subset of a number of available lanes on the serial link. The method also includes selecting to change a transmission state of a second number of lanes. The second number of lanes are a subset of the available lanes. The method also includes changing the transmission state of the second number of lanes while transmitting data on a number of remaining lanes. The method further includes synchronizing the first number of lanes and the second number of lanes.

Abstract: Examples disclose a method, memory component, and storage medium to configure a data width of the memory component. The examples disclose receiving a configuration transaction at the memory component capable to communicate at multiple data widths. Additionally, the examples disclose configuring the data width of the memory component based on the configuration transaction.

Abstract: A computing system can include a memory controller and a first storage device. The first storage device is to receive a serially encoded request and forward the serially encoded request to a second storage device before deserializing the serially encoded request. The first storage device is also to return a training sequence from the target storage device to the memory controller. The first storage device is additionally to return a response from the target storage device to the memory controller.

Abstract: A computing system can include a memory controller and a first storage device. The first storage device is to receive a serially encoded request and forward the serially encoded request to a second storage device before deserializing the serially encoded request. The first storage device is also to return a training sequence from the target storage device to the memory controller. The first storage device is additionally to return a response from the target storage device to the memory controller.

Abstract: A method and a corresponding apparatus for verifying a minimal level sensitive timing abstraction model provides for an extension of the timing abstraction model. The method modifies and runs the timing abstraction model with certain stimulus to establish whether the timing results with the timing abstraction model are identical to the timing result with the modeled circuit. The timing abstraction model extension, which enables verification of the timing abstraction model, only negligibly increases the size of the timing abstraction model, thus keeping STA runtimes short and the memory requirements small.

Abstract: A method and a corresponding apparatus provides for modeling circuit environmental sensitivity for a basic minimal level sensitive timing abstraction model. Environmental issues typically include different external conditions, such as input signal switching time and output capacitive loading for the circuit, that are influenced by the circuitry surrounding the basic timing abstraction model. The method for modeling circuit environmental sensitivity involves creation of delay components that allow for modeling the circuit environmental sensitivities while maintaining the transparent regions of the circuit. To properly model the environment effects, zero delay elements may be inserted at input and output ports of the basic timing abstraction model, producing an improved abstraction model that retains accuracy and efficiency of the basic timing abstraction model.

Abstract: A method for improved load sensitivity modeling in a minimal level sensitive timing abstraction model provides for an extension of the timing abstraction model. The timing abstraction model extension improves accuracy of the timing abstraction model by splitting setup/hold check nodes and/or dummy latch nodes at certain input and/or output ports.

Abstract: A minimal level sensitive timing abstraction model supports multiple levels of hierarchy, is input stimulus independent, can be input into general static timing analysis (STA) tools, and limits timing analysis to the most critical paths, i.e., the most critical arrival at any given port, leading to significant reduction of the number of internal clock-controlled nodes, which in turn results in significant speed-up of STA runs on large circuits and reduced memory and storage space requirements. Further speed-up of STA runs may be achieved by tracing only the most relevant transparent paths to a given output port, which reduces the number of paths fed to the adjacent blocks. The timing abstraction model may also simplify the output from the timing analysis and may shorten designer's time to analyze STA results.

Abstract: A minimal level sensitive timing representative of a circuit path uses a circuit path timing model to represent a circuit block, which contains multiple circuit paths, in a simplified form, thus reducing the circuit paths to a minimized representation with same timing requirements and fixed clock waveforms. The reduction of the circuit paths in turn results in significant speed-up of static timing analysis (STA) runs on large circuits and reduced memory and storage space requirements. The minimal level sensitive timing representative may simplifies the output from the timing analysis and shortens designer's time to analyze STA results.