Abstract: A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.

Abstract: A method for managing a multi-lane serial link is described. The method includes establishing a serial link between a number of integrated circuits across a first number of lanes. The first number of lanes are a subset of a number of available lanes on the serial link. The method also includes selecting to change a transmission state of a second number of lanes. The second number of lanes are a subset of the available lanes. The method also includes changing the transmission state of the second number of lanes while transmitting data on a number of remaining lanes. The method further includes synchronizing the first number of lanes and the second number of lanes.

Abstract: An example device in accordance with an aspect of the present disclosure includes at least one current comparator, a plurality of threshold currents, and a controller. The current comparator is to compare a memristor current to a plurality of threshold currents. The controller is to set a desired memristance state of a memristor according to a memristance feedback tuning loop based on a plurality of threshold levels. The controller is to apply positive and negative voltages to the memristor during the feedback tuning loop to achieve the desired memristance state of the memristor.

Abstract: The present disclosure provides a data storage device that includes a memory cell array and sense circuitry to detect a data value stored to a memory cell of the memory cell array. The data storage device also includes a controller to bias the sense circuitry during a read phase of a write operation to increase the probability that the sense circuitry will detect an opposite value that, is opposite from the value being written to the memory cell.

Abstract: Example implementations relate to memory read requests. For example, an implementation may include tracking progress of an iterative write sequence to write data to a memory element of a memory module. A received read request is detected to be addressed to a memory bank that includes the memory element undergoing the iterative write sequence. Based on the tracked progress, a time is determined to interrupt the iterative write sequence with insertion of the read request. The time aligns between operations of the iterative write sequence and data is returned within a predetermined read latency.

Abstract: A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator concurrently applies a read voltage to the resistive memory cell and the reference cell via a memory row address. A sensing circuit enables the function generator and monitors a target current received from the resistive memory cell when selected via a memory column address and monitors a reference current received when selected via a reference column address in response to the read voltage applied to the memory row address. A current comparator circuit in the sensing circuit compares a difference between the target current and the reference current to determine the memory state of the resistive memory cell.

Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.

Abstract: A method is provided. In an example, the method includes identifying a memory module that includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a plurality of memory regions, and each memory die of the plurality of memory dies services a respective portion of a data access. An error pattern is detected in a first memory region of the plurality of memory regions. The first memory region is associated with a first memory die of the plurality of memory dies. Based on the detected error pattern, the first memory region of the first memory die is marked as erased without marking a second memory region of the first memory die as erased.

Abstract: In an example, a method of controlling a memristor memory includes operating the memristor memory in a volatile mode, wherein switching a state of a memristor cell is with a low writing load. The method also includes operating the same memristor memory in a non-volatile mode, wherein switching a state of the memristor cell is with a high writing load.

Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.

Abstract: An example device in accordance with an aspect of the present disclosure includes at least one current comparator, a plurality of threshold currents, and a controller. The current comparator is to compare a memristor current to a plurality of threshold currents. The controller is to set a desired memristance state of a memristor according to a memristance feedback tuning loop based on a plurality of threshold levels. The controller is to apply positive and negative voltages to the memristor during the feedback tuning loop to achieve the desired memristance state of the memristor.

Abstract: In various examples, a device comprises a memory. The memory comprises a plurality of dies and logic. The logic may: determine a tolerable bit error rate (BER) of the memory based on whether one of the plurality of dies has failed, and adjust a parameter of the memory based on the tolerable BER.

Abstract: In various examples, a memory may comprise a first subarray having an associated first staging buffer, a second subarray having an associated second staging buffer, and request logic. The request logic may: receive a first write request associated with the first subarray, receive a second write request associated with the second subarray, store the first write request in the first staging buffer, store the second write request in the second staging buffer, and execute the first write request and the second write request.

Abstract: In various examples, a memory may comprise a subarray having an associated write extension buffer; and request logic to; receive a write request associated with the subarray, execute the write request. The request logic may further determine that the write request has not completed within an allocated number of write cycles, and responsive to determining that the write request has not completed the allocated number of write cycles: store the write request in the write extension buffer.

Abstract: A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.

Abstract: A method of determining a current in a memory element of a crossbar array is described. In the method, a number of pre-access operations are initiated. Each pre-access operation includes discarding a previously stored sneak current, determining a new sneak current for the crossbar array, discarding a previously stored sneak current, and storing the new sneak current. In the method, in response to a received access command, an access voltage is applied to a target memory element of the crossbar array and an element current for the target memory element is determined based on an access current and a stored sneak current.

Abstract: An integrated circuit is provided. In an example, the integrated circuit includes a first address line, a selector device electrically coupled to the first address lines, and a memory device electrically coupled between the selector device and a second address line. The selector device has a first I-V response in a first current direction and a second I-V response in a second current direction that is different from the first I-V response.

Abstract: An apparatus includes a first resistive storage element and a second resistive storage element. The first and second resistive storage elements are coupled to column lines to of a crosspoint array to form a memory cell; and a ratio of resistances of the first and second resistive storage elements indicates a stored value for the memory cell.

Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.

Abstract: A method for managing data using a number of non-volatile memory arrays is described. The method includes writing data from a volatile memory region to a first non-volatile memory array. The method also includes writing a remaining portion of the data from the volatile memory region to a second non-volatile memory array in response to detecting that an event has occurred. The second non-volatile memory array has a lower write latency than the first non-volatile memory array.