Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.

Abstract: According to an example, a dual in-line memory module (DIMM) may include a high density package substrate including a plurality of connectors for communicatively interconnecting the DIMM to a system.

Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state.

Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state.

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

Abstract: In various examples, a device comprises a memory. The memory comprises a plurality of dies and logic. The logic may: determine a tolerable bit error rate (BER) of the memory based on whether one of the plurality of dies has failed, and adjust a parameter of the memory based on the tolerable BER.

Abstract: Devices and methods are provided, In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

Abstract: Examples described herein relate to a security system consistent with the disclosure. For instance, the security system may comprise a sensor interface bridge connecting a gateway to an input/output (I/O) card, a Field Programmable Gate Array (FPGA) to scan data to detect an anomaly in the data while the data is in the sensor interface bridge, where a learning neural network accelerator Application-Specific Integrated Circuit (ASIC) is integrated with the FPGA and send the data without an anomaly to the gateway.

Abstract: A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.

Abstract: Example implementations relate to memory read requests. For example, an implementation may include tracking progress of an iterative write sequence to write data to a memory element of a memory module. A received read request is detected to be addressed to a memory bank that includes the memory element undergoing the iterative write sequence. Based on the tracked progress, a time is determined to interrupt the iterative write sequence with insertion of the read request. The time aligns between operations of the iterative write sequence and data is returned within a predetermined read latency.

Abstract: A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.

Abstract: According to an example, a dual in-line memory module (DIMM) may include a high density package substrate including a plurality of connectors for communicatively interconnecting the DIMM to a system.

Abstract: Disclosed techniques provide for dynamically changing precision of a multi-stage compute process. For example, changing neural network (NN) parameters on a per-layer basis depending on properties of incoming data streams and per-layer performance of an NN among other considerations. NNs include multiple layers that may each be calculated with a different degree of accuracy and therefore, compute resource overhead (e.g., memory, processor resources, etc.). NNs are usually trained with 32-bit or 16-bit floating-point numbers. Once trained, an NN may be deployed in production. One approach to reduce compute overhead is to reduce parameter precision of NNs to 16 or 8 for deployment. The conversion to an acceptable lower precision is usually determined manually before deployment and precision levels are fixed while deployed.

Abstract: A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator concurrently applies a read voltage to the resistive memory cell and the reference cell via a memory row address. A sensing circuit enables the function generator and monitors a target current received from the resistive memory cell when selected via a memory column address and monitors a reference current received when selected via a reference column address in response to the read voltage applied to the memory row address. A current comparator circuit in the sensing circuit compares a difference between the target current and the reference current to determine the memory state of the resistive memory cell.

Abstract: A data storage device includes a memory cell array and sense circuitry to detect a data value stored to a memory cell of the memory cell array. The data storage device also includes a controller to bias the sense circuitry during a read phase of a write operation to increase the probability that the sense circuitry will detect an opposite value that is opposite from the value being written to the memory cell.

Abstract: A dot-product engine (DPE) implemented on an integrated circuit as a crossbar array (CA) includes memory elements comprising a memristor and a transistor in series. A crossbar with N rows, M columns may have N×M memory elements. A vector input for N voltage inputs to the CA and a vector output for M voltage outputs from the CA. An analog-to-digital converter (ADC) and/or a digital-to-analog converter (DAC) may be coupled to each input/output register. Values representing a first matrix may be stored in the CA. Voltages/currents representing a second matrix may be applied to the crossbar. Ohm's Law and Kirchoff's Law may be used to determine values representing the dot-product as read from the crossbar. A portion of the crossbar may perform Error-correcting Codes (ECC) concurrently with calculating the dot-product results. ECC codes may be used to only indicate detection of errors, or for both detection and correction of results.

Abstract: A method for managing data using a number of non-volatile memory arrays is described. The method includes writing data from a volatile memory region to a first non-volatile memory array. The method also includes writing a remaining portion of the data from the volatile memory region to a second non-volatile memory array in response to detecting that an event has occurred. The second non-volatile memory array has a lower write latency than the first non-volatile memory array.

Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.

Abstract: A method is provided. In an example, the method includes identifying a memory module that includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a plurality of memory regions, and each memory die of the plurality of memory dies services a respective portion of a data access. An error pattern is detected in a first memory region of the plurality of memory regions. The first memory region is associated with a first memory die of the plurality of memory dies. Based on the detected error pattern, the first memory region of the first memory die is marked as erased without marking a second memory region of the first memory die as erased.