Abstract: An apparatus include a device substrate having an upper surface, and a frame layer having an upper surface. The frame layer is disposed over the upper surface of the device substrate, and a first opening exists in the frame layer. The apparatus also includes a seed layer disposed over the device substrate and substantially bounded by the first opening; and a lid layer having an upper surface. The lid layer is disposed over the upper surface of the frame layer. A second opening exists in the lid layer, and the second opening is aligned with the first opening. The apparatus also includes an electrically and thermally conductive pillar disposed in the first opening and the second opening.

Abstract: An apparatus include a device substrate having an upper surface, and a frame layer having an upper surface. The frame layer is disposed over the upper surface of the device substrate, and a first opening exists in the frame layer. The apparatus also includes a seed layer disposed over the device substrate and substantially bounded by the first opening; and a lid layer having an upper surface. The lid layer is disposed over the upper surface of the frame layer. A second opening exists in the lid layer, and the second opening is aligned with the first opening. The apparatus also includes an electrically and thermally conductive pillar disposed in the first opening and the second opening.

Abstract: A method for housing an electronic component in a device package includes providing a first substrate, wherein the electronic component is arranged in a component area on a first main surface of the first substrate, and wherein first contact pads are arranged outside of the component area, forming an open top frame structure around the component area on the first main surface of the first substrate, providing a second substrate having second contact pads, arranged symmetrically to the first contact pads and electrically and mechanically connecting the first main surface of the first substrate with the first main surface of the second substrate, so that the frame structure and the second substrate from a cavity or recess around the electronic component on the first substrate.

Abstract: An apparatus comprises a substrate having a trap rich surface layer produced by mechanically grinding a surface of the substrate, an electrical contact disposed on the trap rich surface layer of the substrate, and an electronic device electrically connected to the electrical contact.

Abstract: A device with contact elements. One embodiment provides an electrical device including a structure defining a main face. The structure includes an array of cavities and an array of overhang regions, each overhang region defining an opening to one of the cavities. The electrical device further includes an array of contact elements, each contact element only partially filling one of the cavities and protruding from the structure over the main face.

Abstract: It is proposed a method of manufacturing an electronic system wherein a first substrate comprising first connection elements on a first surface of the first substrate is provided; a second substrate comprising second connection elements on a first surface of the second substrate is provided; a polymer layer is applied to at least one of the two first surfaces; the first connection elements are attached to the second connection elements; and the polymer layer is caused to swell during or after the attachment.

Abstract: An apparatus comprises a device layer structure, a device integrated into the device layer structure, an insulating carrier substrate and an insulating layer being continuously positioned between the device layer structure and the insulating carrier substrate, the insulating layer having a thickness which is less than 1/10 of a thickness of the insulating carrier substrate. An apparatus further comprises a device integrated into a device layer structure disposed on an insulating layer, a housing layer disposed on the device layer structure and housing the device, a contact providing an electrical connection between the device and a surface of the housing layer opposed to the device layer structure and a molding material surrounding the housing layer and the insulating layer, the molding material directly abutting on a surface of the insulating layer being opposed to the device layer structure.

Abstract: A method for housing an electronic component in a device package includes providing a first substrate, wherein the electronic component is arranged in a component area on a first main surface of the first substrate, and wherein first contact pads are arranged outside of the component area, forming an open top frame structure around the component area on the first main surface of the first substrate, providing a second substrate having second contact pads, arranged symmetrically to the first contact pads and electrically and mechanically connecting the first main surface of the first substrate with the first main surface of the second substrate, so that the frame structure and the second substrate from a cavity or recess around the electronic component on the first substrate.

Abstract: A method for housing an electronic component in a device package includes providing a first substrate, wherein the electronic component is arranged in a component area on a first main surface of the first substrate, and wherein first contact pads are arranged outside of the component area, forming an open top frame structure around the component area on the first main surface of the first substrate, providing a second substrate having second contact pads, arranged symmetrically to the first contact pads and electrically and mechanically connecting the first main surface of the first substrate with the first main surface of the second substrate, so that the frame structure and the second substrate from a cavity or recess around the electronic component on the first substrate.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: A device with contact elements. One embodiment provides an electrical device including a structure defining a main face. The structure includes an array of cavities and an array of overhang regions, each overhang region defining an opening to one of the cavities. The electrical device further includes an array of contact elements, each contact element only partially filling one of the cavities and protruding from the structure over the main face.

Abstract: A method for developing a photoresist includes applying a first developer to the photoresist to remove non-cross-linked areas of the photoresist, and applying a second developer to the photoresist to remove remaining non-cross-linked areas of the photoresist, wherein the first developer and the second developer differ in their compositions.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: A semiconductor is disclosed. In one embodiment, the semiconductor includes a semiconductor substrate having an active area region, a covering configured to protect the active area region, and a carrier. An interspace is located between the carrier and the covering. The interspace is filled with an underfiller material is disclosed.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: An apparatus comprises a device layer structure, a device integrated into the device layer structure, an insulating carrier substrate and an insulating layer being continuously positioned between the device layer structure and the insulating carrier substrate, the insulating layer having a thickness which is less than 1/10 of a thickness of the insulating carrier substrate. An apparatus further comprises a device integrated into a device layer structure disposed on an insulating layer, a housing layer disposed on the device layer structure and housing the device, a contact providing an electrical connection between the device and a surface of the housing layer opposed to the device layer structure and a molding material surrounding the housing layer and the insulating layer, the molding material directly abutting on a surface of the insulating layer being opposed to the device layer structure.

Abstract: An apparatus comprises a device layer structure, a device integrated into the device layer structure, an insulating carrier substrate and an insulating layer being continuously positioned between the device layer structure and the insulating carrier substrate, the insulating layer having a thickness which is less than 1/10 of a thickness of the insulating carrier substrate. An apparatus further comprises a device integrated into a device layer structure disposed on an insulating layer, a housing layer disposed on the device layer structure and housing the device, a contact providing an electrical connection between the device and a surface of the housing layer opposed to the device layer structure and a molding material surrounding the housing layer and the insulating layer, the molding material directly abutting on a surface of the insulating layer being opposed to the device layer structure.

Abstract: An integrated circuit that comprises a substrate and a structured layer on the substrate. The structured layer comprises an opening to the substrate, a first field and a second field on the substrate, wherein the first field and the second field, at least in part, overlap with the opening. The integrated circuit further comprises a first material in the area of the first field and a second material in the area of the second field. The first material impedes a wetting by a solder material, and the second provides a wetting by the solder material.