Patents by Inventor Martin Franosch
Martin Franosch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060183325Abstract: A lift-off method includes providing a material structure, applying photoresist on a surface of the material structure, partially exposing the photoresist, baking the material structure with the partially exposed photoresist applied on the surface of the material structure, developing the photoresist with an organic, polar developer, so that the photoresist is removed in a first region of the surface, and the photoresist remains in the second region of the surface, applying coating material on the surface of the material structure and the remaining photoresist, and removing the photoresist.Type: ApplicationFiled: January 12, 2006Publication date: August 17, 2006Applicant: Infineon Technologies AGInventors: Martin Franosch, Klaus-Guenter Oppermann
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Patent number: 7064360Abstract: A method is provided to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be kept low in the base region since no implantations are required in order to reduce the base connection resistance. Furthermore, the difficulties associated with the point defects are largely avoided.Type: GrantFiled: February 4, 2002Date of Patent: June 20, 2006Assignee: Infineon Technologies AGInventors: Martin Franosch, Thomas Meister, Herbert Schaefer, Reinhard Stengl
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Patent number: 6955950Abstract: In a method for generating a protective cover for a device, where a substrate is provided, which comprises the device, first, a sacrificial pattern is generated on the substrate. The sacrificial pattern covers at least an area of the substrate, which comprises the device. Then, a polymer layer is deposited, which comprises at least on sacrificial pattern. Then, an opening will be formed in the polymer layer to expose a portion of the sacrificial pattern. Then, the sacrificial pattern will be removed and the formed opening in the polymer layer is closed.Type: GrantFiled: July 9, 2004Date of Patent: October 18, 2005Assignee: Infineon Technologies AGInventors: Robert Aigner, Martin Franosch, Andreas Meckes, Klaus-Günter Oppermann, Marc Strasser
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Patent number: 6939734Abstract: In a method for producing a protective cover for a device which is formed in a substrate, a first cover layer is initially deposited on the substrate, the first cover layer covering an area of the substrate which includes the device. Subsequently, an opening is formed in the first cover layer, the opening exposing that area of the substrate which includes the device. Then the opening formed in the first cover layer is filled up using a filling material. Subsequently, a second cover layer is deposited on the first cover layer and in the opening of the first cover layer which is filled up with the filling material. Thereafter, an opening is formed in the second cover layer to expose an area of the filling material. Finally, the filling material covering that area of the substrate which includes the device is removed, and the opening formed in the second cover layer is closed.Type: GrantFiled: April 8, 2004Date of Patent: September 6, 2005Assignee: Infineon Technologies AGInventors: Martin Franosch, Andreas Meckes, Klaus-Günter Oppermann
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Publication number: 20050146022Abstract: Apparatus for housing a micromechanical structure, and a method for producing the housing. The apparatus has a substrate having a main side on which the micromechanical structure is formed, a photo-resist material structure surrounding the micromechanical structure to form a cavity together with the substrate between the substrate and the photo-resist material structure, wherein the cavity separates the micromechanical structure and the photo-resist material structure and has an opening, and a closure for closing the opening to close the cavity.Type: ApplicationFiled: November 17, 2004Publication date: July 7, 2005Applicant: Infineon Technologies AGInventors: Martin Franosch, Andreas Meckes, Winfried Nessler, Klaus-Gunter Oppermann
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Publication number: 20050148205Abstract: In a method for producing a protective cover for a device formed in a substrate, at first a sacrificial structure is produced on the substrate, wherein the sacrificial structure comprises a first portion covering a first area of the substrate including the device and a second portion extending from the first portion into a second area of the substrate including no device. Then a first cover layer is deposited that encloses the sacrificial structure such that the second portion of the sacrificial structure is at least partially exposed. Then the sacrificial structure is removed, and the structure formed by the removal of the sacrificial structure is closed.Type: ApplicationFiled: April 9, 2004Publication date: July 7, 2005Applicant: Infineon Technologies AGInventors: Martin Franosch, Andreas Meckes, Klaus-Gunter Oppermann
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Patent number: 6909141Abstract: A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on a base side thereof to a first common electrical contact. The vertical pillar structures include, along the vertical direction, layer zones of differing conductivity, and have insulation layers on their circumferential walls. An electrically conductive material is deposited between the pillar structures and forms a second electrical contact of the semiconductor transistor component. The pillar structures are electrically contacted to a third common electrical contact on their capping side.Type: GrantFiled: January 16, 2002Date of Patent: June 21, 2005Assignee: Infineon Technologies AGInventors: Wolfgang Rösner, Thomas Schulz, Lothar Risch, Thomas Äugle, Herbert Schäfer, Martin Franosch
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Patent number: 6903454Abstract: A contact spring configuration for contacting semiconductor wafers is provided. At least one strip-type contact spring is provided on a substrate. The contact spring is fixed to a surface of the substrate on one side and is composed of a semiconductor material having a stress gradient which causes a permanent bending of the contact spring. The stress gradient in the semiconductor material is brought about by two semiconductor layers which are connected to one another and are mechanically strained differently. The different strains can be set by different doping or by deposition temperatures of different magnitude during the deposition of the semiconductor layers. The contact springs provide a good ohmic contact in particular with contact regions of a semiconductor wafer that are composed of a semiconductor material.Type: GrantFiled: December 20, 2002Date of Patent: June 7, 2005Assignee: Infineon Technologies AGInventors: Matthias Goldbach, Albert Birner, Martin Franosch
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Publication number: 20050079686Abstract: In a method for producing a cover for a region of a substrate, first a frame structure is produced in the region of the substrate, and then a cap structure is attached to the frame structure so that the region under the cap structure is covered. Thus, sensitive devices may be protected easily and at low cost from external influences and particularly from a casting material for casting the entire packaged device, which results when a diced chip is cast.Type: ApplicationFiled: August 18, 2004Publication date: April 14, 2005Applicant: Infineon Technologies AGInventors: Robert Aigner, Martin Franosch, Andreas Meckes, Klaus-Guenter Oppermann, Marc Strasser
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Patent number: 6878600Abstract: A method for fabricating trench capacitors having trenches with mesopores, the trench capacitors being suitable both for discrete capacitors and for integrated semiconductor memories, significantly increases the surface area for electrodes of the capacitors and, hence, the capacitance thereof. The mesopores, which are small woodworm-hole-like channels having diameters from approximately 2 to 50 nm, are fabricated electrochemically. It is, thus, possible to produce capacitances with a large capacitance-to-volume ratio. Growth of the mesopores stops, at the latest, when the mesopores reach a minimum distance from another mesopore or adjacent trench (self-passivation). As such, the formation of “short circuits” between two adjacent mesopores can be avoided in a self-regulated manner. Furthermore, a semiconductor device is provided including at least one trench capacitor on the front side of a semiconductor substrate fabricated by the method according to the invention.Type: GrantFiled: May 12, 2003Date of Patent: April 12, 2005Assignee: Infineon Technologies AGInventors: Albert Birner, Matthias Goldbach, Martin Franosch
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Patent number: 6867105Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.Type: GrantFiled: August 8, 2002Date of Patent: March 15, 2005Assignee: Infineon Technologies AGInventors: Reinhard Stengl, Thomas Meister, Herbert Schäfer, Martin Franosch
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Patent number: 6863769Abstract: A base body is provided, on which a first sealing ring and a second sealing ring are disposed. A substrate is disposed on the sealing rings in such a way that a cavity is formed between the first sealing ring, the second sealing ring, the base body and the substrate. An etching substance can be introduced into the cavity in order to etch clear a conductive layer that has been applied to the substrate. When a conductive layer that has been applied to the substrate back surface has been uncovered, an electrolyte can be introduced into the cavity, making contact with the conductive layer and therefore the substrate back surface.Type: GrantFiled: September 12, 2003Date of Patent: March 8, 2005Assignee: Infineon Technologies AGInventors: Albert Birner, Martin Franosch, Matthias Goldbach, Volker Lehmann, Jörn Lützen
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Publication number: 20050048757Abstract: In a method for generating a protective cover for a device, where a substrate is provided, which comprises the device, first, a sacrificial pattern is generated on the substrate. The sacrificial pattern covers at least an area of the substrate, which comprises the device. Then, a polymer layer is deposited, which comprises at least on sacrificial pattern. Then, an opening will be formed in the polymer layer to expose a portion of the sacrificial pattern. Then, the sacrificial pattern will be removed and the formed opening in the polymer layer is closed.Type: ApplicationFiled: July 9, 2004Publication date: March 3, 2005Applicant: Infineon Technologies AGInventors: Robert Aigner, Martin Franosch, Andreas Meckes, Klaus-Gunter Oppermann, Marc Strasser
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Publication number: 20050009316Abstract: In a method for producing a protective cover for a device which is formed in a substrate, a first cover layer is initially deposited on the substrate, the first cover layer covering an area of the substrate which includes the device. Subsequently, an opening is formed in the first cover layer, the opening exposing that area of the substrate which includes the device. Then the opening formed in the first cover layer is filled up using a filling material. Subsequently, a second cover layer is deposited on the first cover layer and in the opening of the first cover layer which is filled up with the filling material. Thereafter, an opening is formed in the second cover layer to expose an area of the filling material. Finally, the filling material covering that area of the substrate which includes the device is removed, and the opening formed in the second cover layer is closed.Type: ApplicationFiled: April 8, 2004Publication date: January 13, 2005Applicant: Infineon Technologies AGInventors: Martin Franosch, Andreas Meckes, Klaus-Gunter Oppermann
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Publication number: 20050006723Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.Type: ApplicationFiled: August 4, 2004Publication date: January 13, 2005Inventors: Reinhard Stengl, Thomas Meister, Herbert Schafer, Martin Franosch
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Patent number: 6746880Abstract: A method for electrically contacting a rear side of a semiconductor substrate when processing the semiconductor substrate includes the step of placing the semiconductor substrate with a substrate rear side on a substrate holder such that an electrically conductive contact layer formed of a semiconductor material is disposed between the semiconductor substrate and the substrate holder.Type: GrantFiled: May 31, 2001Date of Patent: June 8, 2004Assignee: Infineon Technologies AGInventors: Albert Birner, Martin Franosch, Matthias Goldbach, Volker Lehmann, Jörn Lützen
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Publication number: 20040104402Abstract: A base body is provided, on which a first sealing ring and a second sealing ring are disposed. A substrate is disposed on the sealing rings in such a way that a cavity is formed between the first sealing ring, the second sealing ring, the base body and the substrate. An etching substance can be introduced into the cavity in order to etch clear a conductive layer that has been applied to the substrate. When a conductive layer that has been applied to the substrate back surface has been uncovered, an electrolyte can be introduced into the cavity, making contact with the conductive layer and therefore the substrate back surface.Type: ApplicationFiled: September 12, 2003Publication date: June 3, 2004Inventors: Albert Birner, Martin Franosch, Matthias Goldbach, Volker Lehmann, Jorn Lutzen
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Publication number: 20040099881Abstract: The method according to the invention makes it possible to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be kept low in the base region since no implantations are required in order to reduce the base connection resistance. Furthermore, the difficulties associated with the point defects are largely avoided.Type: ApplicationFiled: December 22, 2003Publication date: May 27, 2004Inventors: Martin Franosch, Thomas Meister, Herbert Schaefer, Reinhard Stengl
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Publication number: 20030201479Abstract: A method for fabricating trench capacitors having trenches with mesopores, the trench capacitors being suitable both for discrete capacitors and for integrated semiconductor memories, significantly increases the surface area for electrodes of the capacitors and, hence, the capacitance thereof. The mesopores, which are small woodworm-hole-like channels having diameters from approximately 2 to 50 nm, are fabricated electrochemically. It is, thus, possible to produce capacitances with a large capacitance-to-volume ratio. Growth of the mesopores stops, at the latest, when the mesopores reach a minimum distance from another mesopore or adjacent trench (self-passivation). As such, the formation of “short circuits” between two adjacent mesopores can be avoided in a self-regulated manner. Furthermore, a semiconductor device is provided including at least one trench capacitor on the front side of a semiconductor substrate fabricated by the method according to the invention.Type: ApplicationFiled: May 12, 2003Publication date: October 30, 2003Inventors: Albert Birner, Matthias Goldbach, Martin Franosch
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Patent number: 6635545Abstract: The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.Type: GrantFiled: June 3, 2002Date of Patent: October 21, 2003Assignee: Infineon Technologies AGInventors: Josef Böck, Wolfgang Klein, Herbert Schäfer, Martin Franosch, Thomas Meister, Reinhard Stengl