Patents by Inventor Martin Poelzl

Martin Poelzl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180138278
    Abstract: A semiconductor device includes a semiconductor body having a main surface and an active region surrounded by a non-active region. A trench extends from the main surface into the semiconductor body. The trench has a stripe configuration and extends laterally within the active region. A first electrode and a first insulator are in the trench. The first insulator insulates the first electrode from the semiconductor body. The first electrode is recessed in the trench and has a planar surface extending generally parallel with and below the main surface of the semiconductor body so as to define a well in the trench that is laterally confined by the first insulator. A second insulator is on the planar surface. A second electrode is within the well of the trench, and the second insulator insulates the second electrode from the first electrode.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 17, 2018
    Inventors: Heimo Hofer, Martin Poelzl, Maximilian Roesch, Britta Wutte
  • Publication number: 20180138120
    Abstract: A semiconductor device includes a semiconductor layer with a thickness of at most 50 ?m. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness. The total thickness, which is the sum of the first thickness and the second thickness, deviates from the thickness of the semiconductor layer by not more than 20% and a difference between the first thickness and the second thickness is not more than 20% of the total thickness.
    Type: Application
    Filed: November 6, 2017
    Publication date: May 17, 2018
    Inventors: Paul Ganitzer, Martin Poelzl
  • Patent number: 9935055
    Abstract: A method of manufacturing a semiconductor device includes forming a separation trench into a first main surface of a semiconductor substrate and removing substrate material from a second main surface of the semiconductor substrate, so as to thin the substrate to a thickness of less than 100 ?m, the second main surface being opposite to the first main surface, so as to uncover a bottom side of the trench. Additional methods of manufacturing semiconductor devices are provided.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: April 3, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Meiser, Markus Zundel, Martin Poelzl, Paul Ganitzer, Georg Ehrentraut
  • Patent number: 9923072
    Abstract: A semiconductor component includes a semiconductor body having a surface and a cutout in the semiconductor body. The cutout extends from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface. The cutout has a base and at least one sidewall. The component further includes a layer on the surface of the semiconductor body and in the cutout. The layer forms a well above the cutout. The well has a well base, a well edge and at least one well sidewall. The at least one well sidewall forms an angle ? in the range of 20° to 80° with respect to the surface of the semiconductor body. The layer has at least one edge which, proceeding from the well edge, extends in the direction of the surface of the semiconductor body.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: March 20, 2018
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Poelzl
  • Patent number: 9917160
    Abstract: A semiconductor device includes a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: March 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andrew Christopher Graeme Wood, Oliver Blank, Martin Poelzl, Martin Vielemeyer
  • Publication number: 20180047719
    Abstract: A method of manufacturing a semiconductor die includes: forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the power HEMT having a gate, a source and a drain; monolithically integrating a first gate driver HEMT with the power HEMT in the III-nitride semiconductor substrate, the first gate driver HEMT having a gate, a source and a drain and logically forming part of a driver; and electrically connecting the first gate driver HEMT to the gate of the power HEMT so that the first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device.
    Type: Application
    Filed: September 19, 2017
    Publication date: February 15, 2018
    Inventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
  • Patent number: 9859385
    Abstract: A method of processing a semiconductor device is presented. The method includes providing a semiconductor body; forming a trench within the semiconductor body, the trench having a stripe configuration and extending laterally within an active region of the semiconductor body that is surrounded by a non-active region of the semiconductor body; forming, within the trench, a first electrode and a first insulator insulating the first electrode from the semiconductor body; carrying out a first etching step for partially removing the first electrode along the total lateral extension of the first electrode such that the remaining part of the first electrode has a planar surface, thereby creating a well in the trench that is laterally confined by the first insulator; depositing a second insulator on top the planar surface; and forming a second electrode within the well of the trench. The second insulator insulates the second electrode from the first electrode.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: January 2, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Heimo Hofer, Martin Poelzl, Maximilian Roesch, Britta Wutte
  • Patent number: 9852945
    Abstract: A semiconductor device is manufactured at least partially in a semiconductor substrate. The substrate has first and second opposing main surfaces. The method includes forming a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, and forming the cell field portion by at least forming a transistor. The method further includes insulating a part of the semiconductor substrate from other substrate portions to form a connection substrate portion, forming an electrode adjacent to the second main surface so as to be in contact with the connection substrate portion, forming an insulating layer over the first main surface, forming a metal layer over the insulating layer, forming a trench in the first main surface, and filling the trench with a conductive material, and electrically coupling the connection substrate portion to the metal layer via the trench.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Meiser, Till Schloesser, Martin Poelzl
  • Publication number: 20170330946
    Abstract: A semiconductor device includes a semiconductor substrate comprising a main surface and a gate electrode in a trench between neighboring semiconductor mesas, The gate electrode is electrically insulated from the neighboring semiconductor mesas by a dielectric layer. The semiconductor device further includes a conductor arranged, at least partially, between neighboring dielectric contact spacers. The conductor has a conductivity greater than a conductivity of the gate electrode, An interface between the conductor and the gate electrode extends along the gate electrode.
    Type: Application
    Filed: July 28, 2017
    Publication date: November 16, 2017
    Inventor: Martin Poelzl
  • Patent number: 9806187
    Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is formed on the horizontal surface. An epitaxial region is formed by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask. The epitaxial region is polished by a chemical-mechanical polishing process stopping on the epitaxy hard mask. A vertical trench is formed in the semiconductor body. An insulated field plate is formed in a lower portion of the vertical trench and an insulated gate electrode is formed above the insulated field plate. Further, a method for forming a field-effect semiconductor device is provided.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: October 31, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Poelzl
  • Publication number: 20170271446
    Abstract: First reinforcement stripes are formed on a process surface of a base substrate. A first epitaxial layer covering the first reinforcement stripes is formed on the first process surface. Second reinforcement stripes are formed on the first epitaxial layer. A second epitaxial layer covering the second reinforcement stripes is formed on exposed portions of the first epitaxial layer. Semiconducting portions of transistor cells are formed in or portions of micro electromechanical structures are formed from the second epitaxial layer.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 21, 2017
    Inventors: Ravi Keshav Joshi, Johannes Baumgartl, Oliver Blank, Oliver Hellmund, Martin Poelzl
  • Patent number: 9768273
    Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 19, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ravi Joshi, Johannes Baumgartl, Martin Poelzl, Matthias Kuenle, Juergen Steinbrenner, Andreas Haghofer, Christoph Gruber, Georg Ehrentraut
  • Publication number: 20170256619
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface, first and second field plate structures extending in a first direction parallel to the first surface, a plurality of gate electrode structures disposed over the first surface and extending in a second direction parallel to the first surface, the second direction being different than the first direction, and a plurality of source regions and drain regions of a first conductivity type arranged in an alternating manner at the first surface so that a drain region is disposed on one side of a gate electrode structure and a source region is disposed on the other side of the gate electrode structure. The gate electrode structures are disposed between the first and the second field plate structures. The source regions and the drain regions extend in parallel with one another along the second direction.
    Type: Application
    Filed: May 19, 2017
    Publication date: September 7, 2017
    Inventor: Martin Poelzl
  • Patent number: 9754859
    Abstract: A semiconductor device includes a semiconductor substrate, a doped zone, a polysilicon layer and an elongate plug structure. The doped zone is within the semiconductor substrate. The polysilicon layer is disposed in a trench electrically isolated from the semiconductor substrate by an insulating layer. The elongate plug structure extends in a lateral direction in or above the semiconductor substrate. The elongate plug structure provides electrical connection between the doped zone and the polysilicon layer.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: September 5, 2017
    Assignee: Infineon Technologies AG
    Inventors: Walter Rieger, Franz Hirler, Martin Poelzl, Manfred Kotek
  • Publication number: 20170236913
    Abstract: A method of processing a semiconductor device includes: creating first and second recesses in a surface of a semiconductor body; creating an insulation layer that forms first and second wells each having a common lateral extension range with the portion of the insulation layer located between the recesses; filling the wells with a plug material having the respective common lateral extension range with the insulation layer; removing a middle portion of the insulation layer located between the recesses; filling, with a filling material, a third recess created in a region where the middle portion has been removed and at least a portion of the space located between the wells; creating a first common surface of the insulation layer, the plug material, and the filling material; removing the plug material from the second well; and creating a second insulation layer that covers a side wall of the second recess.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 17, 2017
    Inventors: Heimo Hofer, Martin Poelzl, Britta Wutte
  • Patent number: 9728617
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a main surface and a gate electrode which is within a trench between neighboring semiconductor mesas. The gate electrode is electrically insulated from the neighboring semiconductor mesas by respective dielectric layers. A respective pillar on each of the neighboring semiconductor mesas is formed, leaving an opening between the pillars above the trench. Dielectric contact spacers are formed in the opening along respective pillar side walls to narrow the opening above the gate electrode. A conductor is formed, having an interface with the gate electrode. The interface extends along an extension of the gate electrode, and the conductor has a conductivity greater than the conductivity of the gate electrode.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Poelzl
  • Publication number: 20170207309
    Abstract: A method of processing a semiconductor device is presented. The method includes providing a semiconductor body; forming a trench within the semiconductor body, the trench having a stripe configuration and extending laterally within an active region of the semiconductor body that is surrounded by a non-active region of the semiconductor body; forming, within the trench, a first electrode and a first insulator insulating the first electrode from the semiconductor body; carrying out a first etching step for partially removing the first electrode along the total lateral extension of the first electrode such that the remaining part of the first electrode has a planar surface, thereby creating a well in the trench that is laterally confined by the first insulator; depositing a second insulator on top the planar surface; and forming a second electrode within the well of the trench. The second insulator insulates the second electrode from the first electrode.
    Type: Application
    Filed: January 13, 2017
    Publication date: July 20, 2017
    Inventors: Heimo Hofer, Martin Poelzl, Maximilian Roesch, Britta Wutte
  • Patent number: 9691862
    Abstract: A semiconductor device includes a field effect transistor in a semiconductor substrate having a first surface. The field effect transistor includes a first field plate structure and a second field plate structure, each extending in a first direction parallel to the first surface, and gate electrode structures disposed over the first surface and extending in a second direction parallel to the first surface, the gate electrode structures being disposed between the first and the second field plate structures.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: June 27, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Poelzl
  • Patent number: 9660055
    Abstract: A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins. The first mask exposes a second area including second stripe and second fin sections. A channel/body zone is formed in the second fin sections by introducing impurities, wherein the first mask is used as an implant mask. Using an etch mask that is based on the first mask, recess grooves are formed at least in the second stripe sections.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Till Schloesser, Andreas Meiser
  • Patent number: 9660047
    Abstract: A method for producing a semiconductor component includes providing a semiconductor body having a first semiconductor material extending to a first surface and at least one trench, the at least one trench extending from the first surface into the semiconductor body, a first insulation layer being arranged in the at least one trench. The method further includes forming a second insulation layer on the first surface having a recess that overlaps in a projection onto the first surface with the at least one trench, forming a mask region in the recess, etching the second insulation layer selectively to the mask region, depositing a third insulation layer over the first surface, and etching the third insulation layer so that a semiconductor mesa of the semiconductor body arranged next to the at least one trench is exposed at the first surface.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Poelzl