Patents by Inventor Martin Poelzl

Martin Poelzl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170125345
    Abstract: A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines includes a resistance section formed of a locally increased specific resistance relative to a specific resistance of adjacent semiconductor material or metal of the respective connection line. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region.
    Type: Application
    Filed: January 12, 2017
    Publication date: May 4, 2017
    Inventors: Gerhard Noebauer, Ralf Siemieniec, Maximilian Roesch, Martin Poelzl, Michael Hutzler
  • Publication number: 20170110331
    Abstract: A method for forming a semiconductor device includes etching, in a masked etching process, through a layer stack located on a surface of a semiconductor substrate to expose the semiconductor substrate at unmasked regions of the layer stack. The method further includes etching, in a selective etching process, at least a first layer of the layer stack located adjacently to the semiconductor substrate. A second layer of the layer stack is less etched or non-etched compared to the selective etching of the first layer of the layer stack, such that the first layer of the layer stack is laterally etched back between the semiconductor substrate and the second layer of the layer stack. The method further includes growing semiconductor material on regions of the surface of the semiconductor substrate exposed after the selective etching process.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 20, 2017
    Inventors: Ravi Keshav Joshi, Johannes Baumgartl, Georg Ehrentraut, Petra Fischer, Richard Gaisberger, Christoph Gruber, Martin Poelzl, Juergen Steinbrenner
  • Patent number: 9620636
    Abstract: A semiconductor device includes field electrode structures regularly arranged in lines in a cell area and forming a first portion of a regular pattern. Termination structures are formed in an inner edge area surrounding the cell area, wherein at least portions of the termination structures form a second portion of the regular pattern. Cell mesas separate neighboring ones of the field electrode structures from each other in the cell area and include first portions of a drift zone, wherein a voltage applied to a gate electrode controls a current flow through the cell mesas. At least one doped region forms a homojunction with the drift zone in the inner edge area.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, Martin Poelzl
  • Patent number: 9590095
    Abstract: A semiconductor device includes field electrode structures regularly arranged in lines in a cell area and forming a first portion of a regular pattern. Termination structures are formed in an inner edge area surrounding the cell area, wherein at least portions of the termination structures form a second portion of the regular pattern. Cell mesas separate neighboring ones of the field electrode structures from each other in the cell area and include first portions of a drift zone, wherein a voltage applied to a gate electrode controls a current flow through the cell mesas. At least one doped region forms a homojunction with the drift zone in the inner edge area.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: March 7, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, Martin Poelzl
  • Patent number: 9583565
    Abstract: A method for manufacturing a semiconductor device comprises includes providing a substrate with a surface, forming an isolating layer on part of the surface, and forming a first semiconductor portion and spaced therefrom a second semiconductor portion on the surface of the substrate. The isolating layer is interposed between a side surface of the first semiconductor portion and a side surface of the second semiconductor portion which face each other. The method further includes forming a first side isolation layer on the side surface of the first semiconductor portion.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: February 28, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Poelzl
  • Patent number: 9570553
    Abstract: A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines has a resistance section that is formed of at least one of: a locally reduced cross-sectional area of the connection line section; and a locally increased specific resistance. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: February 14, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Noebauer, Ralf Siemieniec, Maximilian Roesch, Martin Poelzl, Michael Hutzler
  • Publication number: 20170011927
    Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 12, 2017
    Inventors: Juergen Steinbrenner, Markus Kahn, Helmut Schoenherr, Ravi Joshi, Heimo Hofer, Martin Poelzl, Harald Huetter
  • Publication number: 20170012002
    Abstract: A method of manufacturing a semiconductor device includes forming a separation trench into a first main surface of a semiconductor substrate and removing substrate material from a second main surface of the semiconductor substrate, so as to thin the substrate to a thickness of less than 100 ?m, the second main surface being opposite to the first main surface, so as to uncover a bottom side of the trench. Additional methods of manufacturing semiconductor devices are provided.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 12, 2017
    Inventors: Andreas Meiser, Markus Zundel, Martin Poelzl, Paul Ganitzer, Georg Ehrentraut
  • Publication number: 20170005091
    Abstract: A semiconductor device includes a semiconductor laminar structure arranged on a semiconductor substrate. The semiconductor laminar structure includes a first doping region of a field effect transistor structure and at least a part of a body region of the field effect transistor structure. The body region has a first conductivity type and the first doping region has a second conductivity type. The semiconductor device further includes an electrically conductive contact structure providing an electrical contact to the first doping region of the field effect transistor structure and to the body region of the field effect transistor structure at one or more sidewalls of the semiconductor laminar structure.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 5, 2017
    Inventors: Ravi Keshav Joshi, Johannes Baumgartl, Christoph Gruber, Andreas Haghofer, Martin Poelzl, Juergen Steinbrenner
  • Patent number: 9530773
    Abstract: Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments, the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap diode, or the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap transistor. The bootstrap capacitor comprises a semiconductor-based capacitor, as opposed to an electrolytic, ceramic or other capacitor, in embodiments. The integration of the bootstrap circuit with another circuit or device, such as a power transistor device in one embodiment, is at a silicon-level in embodiments, rather than as a module-like system-in-package of conventional approaches. In other words, the combination of the bootstrap circuit elements and power transistor or other device forms a system-on-silicon, or an integrated circuit, in embodiments, and additionally can be arranged in a single package.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: December 27, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Vielemeyer, Sylvain Leomant, Milko Paolucci, Martin Poelzl
  • Patent number: 9530847
    Abstract: A semiconductor device includes a field electrode structure that includes a field electrode and a field dielectric surrounding the field electrode. The field dielectric includes a first dielectric layer and a second dielectric layer having a smaller band gap and/or a lower conduction band edge than the first dielectric layer. A semiconductor body includes a transistor section that surrounds the field electrode structure and directly adjoins the first dielectric layer. The transistor section includes a source zone, a first drift zone section and a body zone separating the source zone and the first drift zone section. The body zone forms a first pn junction with the source zone and a second pn junction with the first drift zone section.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: December 27, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Martin Poelzl
  • Publication number: 20160308028
    Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.
    Type: Application
    Filed: June 20, 2016
    Publication date: October 20, 2016
    Inventors: Ravi Joshi, Johannes Baumgartl, Martin Poelzl, Matthias Kuenle, Juergen Steinbrenner, Andreas Haghofer, Christoph Gruber, Georg Ehrentraut
  • Patent number: 9461004
    Abstract: A semiconductor workpiece includes a semiconductor substrate, at least two chip areas, components of semiconductor devices being formed in the semiconductor substrate in the at least two chip areas, and a separation trench disposed between adjacent chip areas. The separation trench is formed in a first main surface of the semiconductor substrate and extends from the first main surface to a second main surface of the semiconductor substrate. The second main surface is disposed opposite to the first main surface. The separation trench is filled with at least one sacrificial material.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: October 4, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Meiser, Markus Zundel, Martin Poelzl, Paul Ganitzer, Georg Ehrentraut
  • Patent number: 9455136
    Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: September 27, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Juergen Steinbrenner, Markus Kahn, Helmut Schoenherr, Ravi Joshi, Heimo Hofer, Martin Poelzl, Harald Huetter
  • Patent number: 9431392
    Abstract: A transistor device includes at least one first type transistor cell including a drift region, a source region, a body region arranged between the source region and the drift region, a drain region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. A gate terminal is coupled to the gate electrode, a source terminal is coupled to the source region, and a control terminal is configured to receive a control signal. A variable resistor is connected between the field electrode and the gate terminal or the source terminal. The variable resistor includes a variable resistance configured to be adjusted by the control signal received at the control terminal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 30, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Walter Rieger, Hans Weber, Michael Treu, Gerhard Nöbauer, Martin Pölzl, Martin Vielemeyer, Franz Hirler
  • Publication number: 20160233308
    Abstract: A semiconductor device includes a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.
    Type: Application
    Filed: April 14, 2016
    Publication date: August 11, 2016
    Inventors: Andrew Christopher Graeme Wood, Oliver Blank, Martin Poelzl, Martin Vielemeyer
  • Publication number: 20160218002
    Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.
    Type: Application
    Filed: January 23, 2015
    Publication date: July 28, 2016
    Inventors: Juergen Steinbrenner, Markus Kahn, Helmut Schoenherr, Ravi Joshi, Heimo Hofer, Martin Poelzl, Harald Huetter
  • Publication number: 20160204210
    Abstract: A semiconductor device includes a field effect transistor in a semiconductor substrate having a first surface. The field effect transistor includes a first field plate structure and a second field plate structure, each extending in a first direction parallel to the first surface, and gate electrode structures disposed over the first surface and extending in a second direction parallel to the first surface, the gate electrode structures being disposed between the first and the second field plate structures.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 14, 2016
    Inventor: Martin Poelzl
  • Publication number: 20160190256
    Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 30, 2016
    Inventors: Martin Vielemeyer, Andreas Meiser, Till Schloesser, Franz Hirler, Martin Poelzl
  • Patent number: 9379196
    Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: June 28, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ravi Joshi, Johannes Baumgartl, Martin Poelzl, Matthias Kuenle, Juergen Steinbrenner, Andreas Haghofer, Christoph Gruber, Georg Ehrentraut