Patents by Inventor Martin Poelzl

Martin Poelzl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160181402
    Abstract: A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins. The first mask exposes a second area including second stripe and second fin sections. A channel/body zone is formed in the second fin sections by introducing impurities, wherein the first mask is used as an implant mask. Using an etch mask that is based on the first mask, recess grooves are formed at least in the second stripe sections.
    Type: Application
    Filed: March 1, 2016
    Publication date: June 23, 2016
    Inventors: Martin Poelzl, Till Schloesser, Andreas Meiser
  • Patent number: 9355957
    Abstract: A semiconductor device includes subsurface structures extending from a main surface into a semiconductor portion, each subsurface structure including a gate electrode dielectrically insulated from the semiconductor portion. The semiconductor device further includes alignment plugs in a vertical projection of the subsurface structures, contact spacers extending along sidewalls of the alignment plugs tilted to the main surface, and contact plugs directly adjoining semiconductor mesas between the subsurface structures. The contact plugs are provided between opposing ones of the contact spacers.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: May 31, 2016
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Poelzl
  • Patent number: 9356141
    Abstract: The disclosure relates to a semiconductor device including a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: May 31, 2016
    Assignee: Infineon Technologies AG
    Inventors: Andrew Christopher Graeme Wood, Oliver Blank, Martin Poelzl, Martin Vielemeyer
  • Publication number: 20160141380
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a main surface and a gate electrode which is within a trench between neighboring semiconductor mesas. The gate electrode is electrically insulated from the neighboring semiconductor mesas by respective dielectric layers. A respective pillar on each of the neighboring semiconductor mesas is formed, leaving an opening between the pillars above the trench. Dielectric contact spacers are formed in the opening along respective pillar side walls to narrow the opening above the gate electrode. A conductor is formed, having an interface with the gate electrode. The interface extends along an extension of the gate electrode, and the conductor has a conductivity greater than the conductivity of the gate electrode.
    Type: Application
    Filed: November 6, 2015
    Publication date: May 19, 2016
    Inventor: Martin Poelzl
  • Publication number: 20160111504
    Abstract: First trenches extend from a process surface into a semiconductor layer. An alignment layer with mask pits in a with respect to the process surface vertical projection of the first trenches is formed on the process surface. Sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches. The mask pits are filled with an auxiliary material. A gate trench for a gate structure is formed in a mesa section of the semiconductor layer between the first trenches, wherein the auxiliary material is used as an etch mask.
    Type: Application
    Filed: October 13, 2015
    Publication date: April 21, 2016
    Inventors: Martin Poelzl, Oliver Blank, Franz Hirler, Maximilian Roesch, Li Juin Yip
  • Publication number: 20160104797
    Abstract: A semiconductor device comprises a gate electrode in a trench in a semiconductor body. The gate electrode comprises a plurality of gate segments disposed along an extension direction of the trench, the gate segments being connected to neighboring gate segments by means of connection elements. A distance between adjacent gate segments is equal to or smaller than 0.5*L, wherein L denotes a length of each of the gate segments, the length being measured along the extension direction of the trench.
    Type: Application
    Filed: September 30, 2015
    Publication date: April 14, 2016
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Martin Poelzl, Georg Ehrentraut, Franz Hirler, Maximilian Roesch
  • Patent number: 9306058
    Abstract: An integrated circuit includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: April 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Martin Vielemeyer, Andreas Meiser, Till Schloesser, Franz Hirler, Martin Poelzl
  • Publication number: 20160093529
    Abstract: A semiconductor device is manufactured at least partially in a semiconductor substrate. The substrate has first and second opposing main surfaces. The method includes forming a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, and forming the cell field portion by at least forming a transistor. The method further includes insulating a part of the semiconductor substrate from other substrate portions to form a connection substrate portion, forming an electrode adjacent to the second main surface so as to be in contact with the connection substrate portion, forming an insulating layer over the first main surface, forming a metal layer over the insulating layer, forming a trench in the first main surface, and filling the trench with a conductive material, and electrically coupling the connection substrate portion to the metal layer via the trench.
    Type: Application
    Filed: December 8, 2015
    Publication date: March 31, 2016
    Inventors: Andreas Meiser, Till Schloesser, Martin Poelzl
  • Patent number: 9287404
    Abstract: A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins. The first mask exposes a second area including second stripe and second fin sections. A channel/body zone is formed in the second fin sections by introducing impurities, wherein the first mask is used as an implant mask. Using an etch mask that is based on the first mask, recess grooves are formed at least in the second stripe sections.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: March 15, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Till Schloesser, Andreas Meiser
  • Publication number: 20160064547
    Abstract: A semiconductor device includes field electrode structures regularly arranged in lines in a cell area and forming a first portion of a regular pattern. Termination structures are formed in an inner edge area surrounding the cell area, wherein at least portions of the termination structures form a second portion of the regular pattern. Cell mesas separate neighboring ones of the field electrode structures from each other in the cell area and include first portions of a drift zone, wherein a voltage applied to a gate electrode controls a current flow through the cell mesas. At least one doped region forms a homojunction with the drift zone in the inner edge area.
    Type: Application
    Filed: August 18, 2015
    Publication date: March 3, 2016
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, Martin Poelzl
  • Publication number: 20160043072
    Abstract: Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments, the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap diode, or the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap transistor. The bootstrap capacitor comprises a semiconductor-based capacitor, as opposed to an electrolytic, ceramic or other capacitor, in embodiments. The integration of the bootstrap circuit with another circuit or device, such as a power transistor device in one embodiment, is at a silicon-level in embodiments, rather than as a module-like system-in-package of conventional approaches. In other words, the combination of the bootstrap circuit elements and power transistor or other device forms a system-on-silicon, or an integrated circuit, in embodiments, and additionally can be arranged in a single package.
    Type: Application
    Filed: October 20, 2015
    Publication date: February 11, 2016
    Inventors: Martin Vielemeyer, Sylvain Leomant, Milko Paolucci, Martin Poelzl
  • Patent number: 9257532
    Abstract: A method for forming a semiconductor device. One embodiment provides a semiconductor substrate having a trench with a sidewall isolation. The sidewall isolation is removed in a portion of the trench. A gate dielectric is formed on the laid open sidewall. A gate electrode is formed adjacent to the date dielectric. The upper surface of the gate electrode is located at a depth d1 below the surface of the semiconductor substrate. The gate oxide is removed above the gate electrode. An isolation is formed simultaneously on the gate electrode and the semiconductor substrate such that the absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: February 9, 2016
    Assignee: Infineon Technologies AG
    Inventor: Martin Poelzl
  • Publication number: 20160020287
    Abstract: A semiconductor device includes a field electrode structure that includes a field electrode and a field dielectric surrounding the field electrode. The field dielectric includes a first dielectric layer and a second dielectric layer having a smaller band gap and/or a lower conduction band edge than the first dielectric layer. A semiconductor body includes a transistor section that surrounds the field electrode structure and directly adjoins the first dielectric layer. The transistor section includes a source zone, a first drift zone section and a body zone separating the source zone and the first drift zone section. The body zone forms a first pn junction with the source zone and a second pn junction with the first drift zone section.
    Type: Application
    Filed: July 14, 2015
    Publication date: January 21, 2016
    Inventors: Franz Hirler, Martin Poelzl
  • Patent number: 9231100
    Abstract: A semiconductor device is at least partially formed in a semiconductor substrate, the substrate including first and second opposing main surfaces. The semiconductor device includes a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, the cell field portion including at least a transistor. The contact area includes a connection substrate portion insulated from other substrate portions and including a part of the semiconductor substrate, an electrode adjacent to the second main surface and in contact with the connection substrate portion, and a metal layer disposed over the first main surface, the connection substrate portion being electrically coupled to the metal layer to form an ohmic contact between the electrode and metal layer. The connection substrate portion is not electrically coupled to a component of the cell field portion by a conductive material disposed between the first and second main surfaces.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: January 5, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Meiser, Till Schloesser, Martin Poelzl
  • Publication number: 20150357408
    Abstract: A method for manufacturing a semiconductor device comprises includes providing a substrate with a surface, forming an isolating layer on part of the surface, and forming a first semiconductor portion and spaced therefrom a second semiconductor portion on the surface of the substrate. The isolating layer is interposed between a side surface of the first semiconductor portion and a side surface of the second semiconductor portion which face each other. The method further includes forming a first side isolation layer on the side surface of the first semiconductor portion.
    Type: Application
    Filed: June 5, 2015
    Publication date: December 10, 2015
    Inventor: Martin Poelzl
  • Patent number: 9171738
    Abstract: Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments, the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap diode, or the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap transistor. The bootstrap capacitor comprises a semiconductor-based capacitor, as opposed to an electrolytic, ceramic or other capacitor, in embodiments. The integration of the bootstrap circuit with another circuit or device, such as a power transistor device in one embodiment, is at a silicon-level in embodiments, rather than as a module-like system-in-package of conventional approaches. In other words, the combination of the bootstrap circuit elements and power transistor or other device forms a system-on-silicon, or an integrated circuit, in embodiments, and additionally can be arranged in a single package.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: October 27, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Vielemeyer, Sylvain Leomant, Milko Paolucci, Martin Poelzl
  • Publication number: 20150279962
    Abstract: A method for producing a semiconductor component includes providing a semiconductor body having a first semiconductor material extending to a first surface and at least one trench, the at least one trench extending from the first surface into the semiconductor body, a first insulation layer being arranged in the at least one trench. The method further includes forming a second insulation layer on the first surface having a recess that overlaps in a projection onto the first surface with the at least one trench, forming a mask region in the recess, etching the second insulation layer selectively to the mask region, depositing a third insulation layer over the first surface, and etching the third insulation layer so that a semiconductor mesa of the semiconductor body arranged next to the at least one trench is exposed at the first surface.
    Type: Application
    Filed: June 11, 2015
    Publication date: October 1, 2015
    Inventor: Martin Poelzl
  • Publication number: 20150262942
    Abstract: A semiconductor workpiece includes a semiconductor substrate, at least two chip areas, components of semiconductor devices being formed in the semiconductor substrate in the at least two chip areas, and a separation trench disposed between adjacent chip areas. The separation trench is formed in a first main surface of the semiconductor substrate and extends from the first main surface to a second main surface of the semiconductor substrate. The second main surface is disposed opposite to the first main surface. The separation trench is filled with at least one sacrificial material.
    Type: Application
    Filed: May 29, 2015
    Publication date: September 17, 2015
    Inventors: Andreas Meiser, Markus Zundel, Martin Poelzl, Paul Ganitzer, Georg Ehrentraut
  • Publication number: 20150221735
    Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.
    Type: Application
    Filed: February 6, 2014
    Publication date: August 6, 2015
    Inventors: Ravi Joshi, Johannes Baumgartl, Martin Poelzl, Matthias Kuenle, Juergen Steinbrenner, Andreas Haghofer, Christoph Gruber, Georg Ehrentraut
  • Publication number: 20150221590
    Abstract: A semiconductor device includes subsurface structures extending from a main surface into a semiconductor portion, each subsurface structure including a gate electrode dielectrically insulated from the semiconductor portion. The semiconductor device further includes alignment plugs in a vertical projection of the subsurface structures, contact spacers extending along sidewalls of the alignment plugs tilted to the main surface, and contact plugs directly adjoining semiconductor mesas between the subsurface structures. The contact plugs are provided between opposing ones of the contact spacers.
    Type: Application
    Filed: April 14, 2015
    Publication date: August 6, 2015
    Inventor: Martin Poelzl