Patents by Inventor Martin Standing

Martin Standing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11069624
    Abstract: A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: July 20, 2021
    Assignee: Faraday Semi, Inc.
    Inventors: Martin Standing, Parviz Parto
  • Publication number: 20200335446
    Abstract: A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.
    Type: Application
    Filed: April 16, 2020
    Publication date: October 22, 2020
    Inventors: Martin Standing, Parviz Parto
  • Patent number: 10553557
    Abstract: In an embodiment, an electronic component includes a power semiconductor device embedded in a dielectric core layer and at least one contact layer protruding from a first side face of the dielectric core layer. The contact layer includes an electrically insulating layer and at least one contact pad arranged on the electrically insulating layer. The at least one contact pad is electrically coupled with the power semiconductor device.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: February 4, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Marcus Pawley, Andrew Roberts, Robert Clarke
  • Patent number: 10361178
    Abstract: In an embodiment, an interconnection structure includes a first semiconductor device including a conductive stud, a second device including a contact pad, an adhesive layer including an organic component arranged between a distal end of the conductive stud and the contact pad, the adhesive layer coupling the conductive stud to the contact pad, and a conductive layer extending from the conductive stud to the contact pad. The conductive layer has a melting point of at least 600° C.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 23, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Patent number: 10257937
    Abstract: An assembly includes a first laminate electronic component and a second laminate electronic component. The first laminate electronic component includes a first dielectric layer, at least one first semiconductor die embedded in the first dielectric layer and at least one first contact pad including a first conductive via. The second laminate electronic component includes a second dielectric layer, at least one second semiconductor die embedded in the second dielectric layer and at least one second contact pad including a second conductive via. The first conductive via is electrically coupled to the second conductive via by a common conductive layer.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: April 9, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Andrew Roberts
  • Patent number: 10249551
    Abstract: An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, a heat-spreader embedded in a second dielectric layer and a heat-sink thermally coupled to the heat-spreader. The heat-spreader has a higher thermal conductivity in directions substantially parallel to the major surface of the one or more semiconductor dice than in directions substantially perpendicular to the major surface of the one or more semiconductor dice. The heat-sink has a thermal conductivity in directions substantially perpendicular to the major surface of the one or more semiconductor dice that is higher than the thermal conductivity of the heat-spreader in directions substantially perpendicular to the major surface of the one or more semiconductor dice. The heat-spreader and the heat-sink provide a heat dissipation path from the one or more semiconductor dice having a lateral thermal resistance which increases with increasing distance from the one or more semiconductor devices.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 2, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Patent number: 10217688
    Abstract: An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, a heat-spreader embedded in a second dielectric layer and a heat-sink thermally coupled to the heat-spreader. The heat-spreader has a higher thermal conductivity in directions substantially parallel to the major surface of the one or more semiconductor dice than in directions substantially perpendicular to the major surface of the one or more semiconductor dice. The heat-sink has a thermal conductivity in directions substantially perpendicular to the major surface of the one or more semiconductor dice that is higher than the thermal conductivity of the heat-spreader in directions substantially perpendicular to the major surface of the one or more semiconductor dice. The heat-spreader and the heat-sink provide a heat dissipation path from the one or more semiconductor dice having a lateral thermal resistance which increases with increasing distance from the one or more semiconductor devices.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Patent number: 10192846
    Abstract: In an embodiment, a method includes inserting an electronic component including a power semiconductor device embedded in a dielectric core layer into a slot in a side face of a circuit board. The inserting the electronic component causes one or more electrically conductive contacts on one or more surfaces of the electronic component to electrically couple with one or more corresponding electrical contacts arranged on one or more surfaces of the slot.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 29, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Marcus Pawley, Andrew Roberts, Robert Clarke
  • Publication number: 20180366380
    Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.
    Type: Application
    Filed: August 23, 2018
    Publication date: December 20, 2018
    Inventors: Mark Pavier, Andrew N. Sawle, Martin Standing
  • Patent number: 10103076
    Abstract: A method includes coupling a first major surface of a semiconductor die to a metallic body, depositing an insulation body over said semiconductor die, and removing a portion of said insulation body to expose a plurality of electrodes of said semiconductor die on a second major surface of said semiconductor die opposite said first surface. The method further includes forming a plurality of conductive pads over the plurality of electrodes, each conductive pad of said plurality of conductive pads providing an external connection for a respective one of said plurality of electrodes, wherein each conductive pad of said plurality of conductive pads has an area larger than an area of said respective one of said plurality of electrodes to which the respective conforming conductive pad of said plurality of conductive pads is coupled and extending over said insulation body.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: October 16, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Mark Pavier, Andrew N. Sawle, Martin Standing
  • Patent number: 10074616
    Abstract: In an embodiment, a chip protection envelope includes a first dielectric layer including at least one organic component having a decomposition temperature of at least 180° C., a semiconductor die embedded in the first dielectric layer, the semiconductor die having a first surface and a thickness t1. A second dielectric layer is arranged on a first surface of the first dielectric layer, the second dielectric layer including a photodefinable polymer composition, and a conductive layer is arranged on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The conductive layer has a thickness t2, wherein t2?t1/3.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: September 11, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Martin Standing
  • Patent number: 10064287
    Abstract: In an embodiment, a method includes arranging a first carrier on a first major surface of a circuit board such that an electronic component arranged on the first carrier is positioned in an aperture in the circuit board and spaced apart from side walls of the aperture, and arranging a second carrier on a second major surface of the circuit board such that the second carrier covers the electronic component and the aperture, the second major surface of the circuit board opposing the first major surface of the circuit board. The electronic component includes a power semiconductor device embedded in a dielectric core layer and at least one contact pad arranged on a first major surface of the dielectric core layer.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: August 28, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Andrew Roberts
  • Patent number: 10032688
    Abstract: In an embodiment, an electronic component includes a dielectric core layer having a thickness, at least one semiconductor die embedded in the dielectric core layer and electrically coupled to at least one contact pad arranged on a first side of the dielectric core layer, and a heat dissipation layer arranged on a second side of the dielectric core layer and thermally coupled to the semiconductor die. The semiconductor die has a thickness that is substantially equal to, or greater than, or equal to the thickness of the dielectric core layer. The heat dissipation layer includes a material with a substantially isotropic thermal conductivity.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: July 24, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Marcus Pawley
  • Patent number: 9978719
    Abstract: A method includes applying solder paste to a portion of a circuit board, arranging a first contact pad of a first electronic component adjacent the layer of solder paste, the first electronic component comprising a dielectric layer, at least one semiconductor die embedded in the dielectric layer, the at least one first contact pad being electrically coupled to the semiconductor die and arranged on a lower side of the dielectric layer, and at least one second contact pad positioned on an upper side of the dielectric layer, and melting the solder paste to produce a molten solder that flows onto at least one of the first contact pad and the second contact pad of the first electronic component.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Patent number: 9974187
    Abstract: Representative implementations of devices and techniques provide off-board power conversion. A power cable is arranged to distribute power from a power supply to a peripheral component. An active circuit is integrated into the cable, converting the power en route from the power supply to the peripheral component.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: May 15, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Martin Standing, Andrew Roberts, Milko Paolucci
  • Patent number: 9974190
    Abstract: In an embodiment, a method includes arranging a first carrier on a first major surface of a circuit board such that an electronic component arranged on the first carrier is positioned in an aperture in the circuit board and spaced apart from side walls of the aperture, and arranging a second carrier on a second major surface of the circuit board such that the second carrier covers the electronic component and the aperture, the second major surface of the circuit board opposing the first major surface of the circuit board. The electronic component includes a power semiconductor device embedded in a dielectric core layer and at least one contact pad arranged on a first major surface of the dielectric core layer.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: May 15, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Andrew Roberts
  • Patent number: 9917024
    Abstract: In an embodiment, an electronic component includes a dielectric core layer, one or semiconductor dies comprising a first major surface, a first electrode arranged on the first major surface and a second major surface that opposes the first major surface. One or more slots are arranged within the dielectric core layer adjacent the semiconductor die and a redistribution structure electrically couples the first electrode to a component contact pad arranged adjacent the second major surface of the semiconductor die. The semiconductor die is embedded in the dielectric core layer and a portion of the redistribution structure is arranged on side walls of the slot.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: March 13, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Marcus Pawley
  • Publication number: 20180012859
    Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.
    Type: Application
    Filed: September 22, 2017
    Publication date: January 11, 2018
    Inventor: Martin Standing
  • Patent number: 9867277
    Abstract: Representative implementations of devices and techniques provide improved electrical performance of components, such as chip dice, for example, disposed on different layers of a multi-layer printed circuit board (PCB). In an example, the components may be embedded within layers of the PCB. An insulating layer located between two component layers or sets of layers includes a conductive portion that may be strategically located to provide electrical connectivity between the components. The conductive portion may also be arranged to improve thermal conductivity between points of the PCB.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: January 9, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Andrew Roberts
  • Patent number: 9852939
    Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Martin Standing, Andrew Sawle, Matthew P. Elwin, David P. Jones, Martin Carroll, Ian Glenville Wagstaffe