Patents by Inventor Martin Standing

Martin Standing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180012859
    Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.
    Type: Application
    Filed: September 22, 2017
    Publication date: January 11, 2018
    Inventor: Martin Standing
  • Patent number: 9867277
    Abstract: Representative implementations of devices and techniques provide improved electrical performance of components, such as chip dice, for example, disposed on different layers of a multi-layer printed circuit board (PCB). In an example, the components may be embedded within layers of the PCB. An insulating layer located between two component layers or sets of layers includes a conductive portion that may be strategically located to provide electrical connectivity between the components. The conductive portion may also be arranged to improve thermal conductivity between points of the PCB.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: January 9, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Andrew Roberts
  • Patent number: 9852939
    Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Martin Standing, Andrew Sawle, Matthew P. Elwin, David P. Jones, Martin Carroll, Ian Glenville Wagstaffe
  • Patent number: 9852940
    Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Martin Standing, Andrew Sawle, Matthew P. Elwin, David P. Jones, Martin Carroll, Ian Glenville Wagstaffe
  • Patent number: 9837393
    Abstract: According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: December 5, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Martin Standing
  • Patent number: 9831147
    Abstract: In an embodiment, an electronic component includes a first dielectric layer including an organic component having a decomposition temperature of at least 180° C., a semiconductor die embedded in the first dielectric layer, a second dielectric layer arranged on a first surface of the first dielectric layer, the second dielectric layer including a photo definable polymer composition and defining two or more discrete openings having conductive material, and a first substrate arranged on the second dielectric layer and on the conductive material. One or more contact pads are arranged on an outermost surface of the first substrate.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: November 28, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Patent number: 9824977
    Abstract: In one embodiment, a method of fabricating a semiconductor package includes forming a first plurality of die openings on a laminate substrate. The laminate substrate has a front side and an opposite back side. A plurality of first dies is placed within the first plurality of die openings. An integrated spacer is formed around each die of the plurality of first dies. The integrated spacer is disposed in gaps between the laminate substrate and an outer sidewall of each die of the plurality of first dies. The integrated spacer holds the die within the laminate substrate by partially extending over a portion of a top surface of each die of the plurality of first dies. Front side contacts are formed over the front side of the laminate substrate.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: November 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Martin Standing, Andrew Roberts
  • Publication number: 20170317005
    Abstract: An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, a heat-spreader embedded in a second dielectric layer and a heat-sink thermally coupled to the heat-spreader. The heat-spreader has a higher thermal conductivity in directions substantially parallel to the major surface of the one or more semiconductor dice than in directions substantially perpendicular to the major surface of the one or more semiconductor dice. The heat-sink has a thermal conductivity in directions substantially perpendicular to the major surface of the one or more semiconductor dice that is higher than the thermal conductivity of the heat-spreader in directions substantially perpendicular to the major surface of the one or more semiconductor dice. The heat-spreader and the heat-sink provide a heat dissipation path from the one or more semiconductor dice having a lateral thermal resistance which increases with increasing distance from the one or more semiconductor devices.
    Type: Application
    Filed: July 20, 2017
    Publication date: November 2, 2017
    Inventor: Martin Standing
  • Patent number: 9799623
    Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: October 24, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Martin Standing
  • Patent number: 9769928
    Abstract: Representative implementations of devices and techniques provide improved electrical access to components, such as chip dice, for example, disposed within layers of a multi-layer printed circuit board (PCB). One or more insulating layers may be located on either side of a spacer layer containing the components. The insulating layers may have apertures strategically located to provide electrical connectivity between the components and conductive layers of the PCB.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: September 19, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Patent number: 9741635
    Abstract: An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, means for a spreading heat in directions substantially parallel to a major surface of the one or more semiconductor dice embedded in a second dielectric layer and means for dissipating heat in directions substantially perpendicular to the major surface of the one or more semiconductor dice.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: August 22, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Publication number: 20170196118
    Abstract: A power supply includes a plurality of electronic components including one or more of a rectifier and a switching transistor, an input port configured to receive electrical energy from a power source and a circuit board comprising a cavity. At least one of the rectifier and the switching transistor is embedded in the cavity. The cavity is arranged proximal to the input port such that at least a portion of thermal energy generated by one or more of the rectifier and the switching transistor is dissipated from the power supply by way of the input port.
    Type: Application
    Filed: March 21, 2017
    Publication date: July 6, 2017
    Inventor: Martin Standing
  • Publication number: 20170154831
    Abstract: In an embodiment, an electronic component includes a first dielectric layer including an organic component having a decomposition temperature of at least 180° C., a semiconductor die embedded in the first dielectric layer, a second dielectric layer arranged on a first surface of the first dielectric layer, the second dielectric layer including a photo definable polymer composition and defining two or more discrete openings having conductive material, and a first substrate arranged on the second dielectric layer and on the conductive material. One or more contact pads are arranged on an outermost surface of the first substrate.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Inventor: Martin Standing
  • Publication number: 20170154856
    Abstract: In an embodiment, a chip protection envelope includes a first dielectric layer including at least one organic component having a decomposition temperature of at least 180° C., a semiconductor die embedded in the first dielectric layer, the semiconductor die having a first surface and a thickness t1. A second dielectric layer is arranged on a first surface of the first dielectric layer, the second dielectric layer including a photodefinable polymer composition, and a conductive layer is arranged on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The conductive layer has a thickness t2, wherein t2?t1/3.
    Type: Application
    Filed: November 3, 2016
    Publication date: June 1, 2017
    Inventor: Martin Standing
  • Publication number: 20170148692
    Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 25, 2017
    Inventors: Mark Pavier, Andrew N. Sawle, Martin Standing
  • Patent number: 9653370
    Abstract: Embodiments relate to active devices embedded within printed circuit boards (PCBs). In embodiments, the active devices can comprise at least one die, such as a semiconductor die, and coupling elements for mechanically and electrically coupling the active device with one or more layers of the PCB in which the device is embedded. Embodiments thereby provide easy embedding of active devices in PCBs and inexpensive integration with existing PCB technologies and processes.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: May 16, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Andrew Roberts
  • Patent number: 9653322
    Abstract: Representative implementations of devices and techniques provide a semiconductor package comprising a laminate substrate. The laminate substrate includes at least one conductive layer laminated to a surface of an insulating core. The laminate substrate also includes one or more die openings, in which one or more semiconductor die are located.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: May 16, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Andrew Roberts
  • Patent number: 9642289
    Abstract: A power supply includes a plurality of electronic components including one or more of a rectifier and a switching transistor, an input port configured to receive electrical energy from a power source and a circuit board comprising a cavity. At least one of the rectifier and the switching transistor is embedded in the cavity. The cavity is arranged proximal to the input port such that at least a portion of thermal energy generated by one or more of the rectifier and the switching transistor is dissipated from the power supply by way of the input port.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: May 2, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Patent number: 9633951
    Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: April 25, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Mark Pavier, Andrew N. Sawle, Martin Standing
  • Patent number: 9620471
    Abstract: A power semiconductor package that includes a semiconductor die having at least two power electrodes and a conductive clip electrically and mechanically coupled to each power electrode.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Martin Standing, Robert J. Clarke