Patents by Inventor Martin Standing

Martin Standing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Paste for forming an interconnect and interconnect formed from the paste
    Publication number: 20050093164
    Abstract: A paste for forming an interconnect includes a mixture of binder particles, filler particles and flux material, binder particles having a melting temperature that is lower than that of the filler particles, and the proportion of the binder particles and the filler particles being selected such when heat is applied to melt the binder particles the shape of the paste as deposited is substantially retained thereby allowing for the paste to be used for forming interconnect structures.
    Type: Application
    Filed: October 21, 2004
    Publication date: May 5, 2005
    Inventor: Martin Standing
  • Semiconductor device having clips for connecting to external elements
    Patent number: 6841865
    Abstract: A semiconductor device that has a semiconductor die having at least two opposing major electrodes and a control electrode. Conductive clips, each having a base portion and a contact portion, are connected to respective electrodes at their bases by a respective layer of conductive material. A passivation layer is disposed on at least one of the electrodes and surrounds the layers of conductive material. The base portion and the contact portion of one of the clips are connected by an extension, which extends between the major surfaces of the semiconductor die.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: January 11, 2005
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Chip scale surface mounted device and process of manufacture
    Publication number: 20040224438
    Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
    Type: Application
    Filed: June 7, 2004
    Publication date: November 11, 2004
    Applicant: International Rectifier Corporation
    Inventors: Martin Standing, Hazel Deborah Schofield
  • Chip scale surface mounted device and process of manufacture
    Patent number: 6767820
    Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: July 27, 2004
    Assignee: International Rectifier Corporation
    Inventors: Martin Standing, Hazel Deborah Schofield
  • Semiconductor device package
    Publication number: 20040119148
    Abstract: A semiconductor package that includes two circuit boards and at least one semiconductor device which is disposed between the two circuit boards and connected to external connectors disposed on at least one of the circuit boards.
    Type: Application
    Filed: October 1, 2003
    Publication date: June 24, 2004
    Inventor: Martin Standing
  • Flip-chip device having conductive connectors
    Publication number: 20040099941
    Abstract: Semiconductor devices having a passivation layer formed over their major electrodes and individual electrical connectors connected to the electrodes by conductive attach material through openings in the passivation layer are described.
    Type: Application
    Filed: November 27, 2002
    Publication date: May 27, 2004
    Applicant: International Rectifier Corporation
    Inventor: Martin Standing
  • Semiconductor device having clips for connecting to external elements
    Publication number: 20040099940
    Abstract: A semiconductor device that has a semiconductor die having at least two opposing major electrodes and a control electrode. Conductive clips, each having a base portion and a contact portion, are connected to respective electrodes at their bases by a respective layer of conductive material. A passivation layer is disposed on at least one of the electrodes and surrounds the layers of conductive material. The base portion and the contact portion of one of the clips are connected by an extension, which extends between the major surfaces of the semiconductor die.
    Type: Application
    Filed: November 22, 2002
    Publication date: May 27, 2004
    Applicant: International Rectifier Corporation
    Inventor: Martin Standing
  • Chip scale surface mounted device and process of manufacture
    Publication number: 20040038509
    Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
    Type: Application
    Filed: August 5, 2003
    Publication date: February 26, 2004
    Applicant: International Rectifier Corporation
    Inventors: Martin Standing, Hazel Deborah Schofield
  • Chip scale surface mounted device and process of manufacture
    Publication number: 20040026796
    Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
    Type: Application
    Filed: August 5, 2003
    Publication date: February 12, 2004
    Applicant: International Rectifier Corporation
    Inventors: Martin Standing, Hazel Deborah Schofield
  • Semiconductor package including two semiconductor die disposed within a common clip
    Patent number: 6677669
    Abstract: A co-package semiconductor device including an outer clip in the form of a metal can includes also two semiconductor dies, at least one of which uses the outer clip as an electrical connector. An inner clip is used to dispose one of the dies within the outer clip. The inner clip may be insulated from the outer clip by an insulating layer.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: January 13, 2004
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Wafer level underfill and interconnect process
    Publication number: 20030207490
    Abstract: A chip scale package and a method for its manufacture which include providing sticky interconnects on a surface of a semiconductor die, the interconnects being surrounded by a layer of thermal epoxy.
    Type: Application
    Filed: April 22, 2003
    Publication date: November 6, 2003
    Applicant: International Rectifier Corporation
    Inventor: Martin Standing
  • Chip scale surface mounted device and process of manufacture
    Patent number: 6624522
    Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: September 23, 2003
    Assignee: International Rectifier Corporation
    Inventors: Martin Standing, Hazel Deborah Schofield
  • Semiconductor device with co-packaged die
    Publication number: 20030137040
    Abstract: A co-package semiconductor device including an outer clip in the form of a metal can includes also two semiconductor dies, at least one of which uses the outer clip as an electrical connector. An inner clip is used to dispose one of the dies within the outer clip. The inner clip may be insulated from the outer clip by an insulating layer.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 24, 2003
    Inventor: Martin Standing
  • Surface mounted package with die bottom spaced from support board
    Publication number: 20030132531
    Abstract: A semiconductor package according to the present invention includes a metal can which receives in its interior space a MOSFET. The MOSFET so received is oriented such that its drain electrode is facing the bottom of the can and is electrically connected to the same by a layer of conductive epoxy or a solder or the like. The edges of the MOSFET so placed are spaced from the walls of the can. The space between the edges of the MOSFET and the walls of the can is filled with an insulating layer. A surface of the MOSFET is sub-flush below the plane of a substrate by 0.001-0.005 inches to reduce temperature cycling failures.
    Type: Application
    Filed: December 20, 2002
    Publication date: July 17, 2003
    Inventors: Martin Standing, Andrew Neil Sawle
  • Wafer level underfill and interconnect process
    Patent number: 6582990
    Abstract: A chip scale package and a method for its manufacture which include providing sticky interconnects on a surface of a semiconductor die, the interconnects being surrounded by a layer of thermal epoxy.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: June 24, 2003
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Wafer level insulation underfill for die attach
    Patent number: 6573122
    Abstract: A process for forming an insulation underfill for soldering semiconductor die solder balls by a solder paste on conductive traces on a support surface. The process comprises the screen printing or deposition from a syringe of thermoplastic or thermosetting epoxy columns between the solder balls, to a height equal to the standoff height of the die from the support surface. The assembly is first heated to a temperature at which the plastic becomes semifluid and before the area over which it will spread becomes contaminated with flux residue; and is next heated to the solder paste reflow temperature.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: June 3, 2003
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Wafer level underfill and interconnect process
    Publication number: 20030038342
    Abstract: A chip scale package and a method for its manufacture which include providing sticky interconnects on a surface of a semiconductor die, the interconnects being surrounded by a layer of thermal epoxy.
    Type: Application
    Filed: August 20, 2002
    Publication date: February 27, 2003
    Inventor: Martin Standing
  • High voltage semiconductor device housing with increased clearance between housing can and die for improved flux flushing
    Publication number: 20030001247
    Abstract: A semiconductor device is shown and described which includes a metal can that receives a semiconductor die in an interior thereof. The metal can has a recess formed on a top portion thereof. The recess provides rigidity to the top portion of the metal can which allows the wall of the can to be spaced farther apart from the die, thereby providing a much larger open channel which allows for the easier cleaning of flux residue after soldering.
    Type: Application
    Filed: June 12, 2002
    Publication date: January 2, 2003
    Applicant: International Rectifier Corporation
    Inventor: Martin Standing
  • Semiconductor package
    Patent number: D502151
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: February 22, 2005
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Conductive clip for a semiconductor package
    Patent number: D503691
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: April 5, 2005
    Assignee: International Rectifier Corporation
    Inventors: Martin Standing, Hazel Deborah Schofield