Semiconductor package

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Description

FIG. 1 is a front elevational view of a semiconductor package, showing our design;

FIG. 2 is a left side elevational view thereof;

FIG. 3 is a top plan view thereof; and,

FIG. 4 is a rear elevational view thereof.

The broken lines shown in the figures are for illustrative purposes only and form no part of the claimed design.

Claims

The ornamental design for a semiconductor package, as shown and described.

Referenced Cited
U.S. Patent Documents
D379350 May 20, 1997 Kerklaan
5949654 September 7, 1999 Fukuoka
5959846 September 28, 1999 Noguchi et al.
6130483 October 10, 2000 Shizuki et al.
6351027 February 26, 2002 Giboney et al.
6426484 July 30, 2002 Hembree et al.
6646329 November 11, 2003 Estacio et al.
Patent History
Patent number: D502151
Type: Grant
Filed: Sep 2, 2003
Date of Patent: Feb 22, 2005
Assignee: International Rectifier Corporation (El Segundo, CA)
Inventor: Martin Standing (Tonbridge)
Primary Examiner: Stella Reid
Assistant Examiner: Selina Sikder
Attorney: Ostrolenk, Faber, Gerb & Soffen, LLP
Application Number: 29/189,285