Patents by Inventor Masachika Masuda

Masachika Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5723903
    Abstract: Ends of inner leads are disposed in the vicinity of a peripheral end of a semiconductor chip and a portion of an insulating film tape is affixed to a main surface of the semiconductor chip by an adhesive while other portions of the insulating film tape are affixed to portions of the inner leads by an adhesive. Electrode pads provided in the main surface of the semiconductor chip are electrically connected to the ends of the corresponding inner leads by bonding wires, and the semiconductor chip, the inner leads, the electrode pads, the insulating film tape and the bonding wares are sealed by a resin molding. The thickness of the insulating film tape is smaller than a height from the main surface of the semiconductor chip to an apex of the bonding wire. Surfaces of the ends of the inner leads connected to the bonding wires are positioned lower than the main surface of the semiconductor chip and the inner leads are positioned between the main surface and an opposite surface of the semiconductor chip.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 3, 1998
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corporation
    Inventors: Masachika Masuda, Tamaki Wada
  • Patent number: 5446313
    Abstract: Ends of inner leads are disposed in the vicinity of a peripheral end of a semiconductor chip and a portion of an insulating film tape is affixed to a main surface of the semiconductor chip by an adhesive while other portions of the insulating film tape are affixed to portions of the inner leads by an adhesive. Electrode pads provided in the main surface of the semiconductor chip are electrically connected to the ends of the corresponding inner leads by bonding wires, and the semiconductor chip, the inner leads, the electrode pads, the insulating film tape and the bonding wires are sealed by a resin molding. A thickness of the insulating film tape is smaller than a height from the main surface of the semiconductor chip to an apex of the bonding wire. Surfaces of the ends of the inner leads connected to the bonding wires are positioned to be lower than the main surface of the semiconductor chip and the inner leads are positioned between the main surface and an opposite surface of the semiconductor chip.
    Type: Grant
    Filed: May 24, 1993
    Date of Patent: August 29, 1995
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corporation
    Inventors: Masachika Masuda, Tamaki Wada
  • Patent number: 5150193
    Abstract: The present invention consists in that a through hole of large area is provided in a die pad or a tab, thereby to prevent a resin from cracking at the rear surface of a surface-packaging resin package in a high-temperature soldering atmosphere of vapor-phase reflow or the like, whereby a resin-molded surface-packaged IC of high reliability is provided.
    Type: Grant
    Filed: February 11, 1991
    Date of Patent: September 22, 1992
    Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd.
    Inventors: Toshihiro Yasuhara, Masachika Masuda, Gen Murakami, Kunihiko Nishi, Masanori Sakimoto, Ichio Shimizu, Akio Hoshi, Sumio Okada, Tooru Nagamine
  • Patent number: 4994411
    Abstract: A process of producing a semiconductor device involving the steps of providing a lead frame having inner leads spaced from each other and connected together by a connecting portion; bonding a layer of an insulating material to the connecting portion and to surrounding portions of the inner leads; removing the connecting portion and a portion of the layer of insulating material to form end portions of the inner leads which are separated from each other and retained in a spaced arrangement by a remaning portion of the layer of insulating material; joining a semiconductor chip having bonding pads to the end portions of the inner leads; connecting the bonding pads on the semiconductor chip and the inner leads by wires; and encapsulating the semiconductor chip, the remaining portion of the layer of insulating material, the inner leads and the wires within a resin material; a peripheral portion of one face of the semiconductor chip partially overlapping faces of the end portions.
    Type: Grant
    Filed: March 10, 1989
    Date of Patent: February 19, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Takahiro Naito, Gen Murakami, Hiromichi Suzuki, Hajime Sato, Wahei Kitamura, Masachika Masuda
  • Patent number: 4989068
    Abstract: A semiconductor device having a structure in which an insulating resin film or sheet is stuck on the principal surface of a semiconductor chip which is formed with circuits and in which the inner lead portions of a lead frame are arranged on the principal surface of the semiconductor chip through the insulating sheet, is provided in order that the semiconductor chip having the highest possible density of integration may be received placed in a standardized package. The present invention particularly features the shape of the lead frame, according to which the inner lead portions lying within a sealing member are substantially entirely arrayed over the semiconductor chip itself.
    Type: Grant
    Filed: February 6, 1989
    Date of Patent: January 29, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Toshihiro Yasuhara, Masachika Masuda, Gen Murakami
  • Patent number: 4987474
    Abstract: In a tabless lead frame wherein a space for laying inner leads is sufficiently secured when a lengthened and enlarged semiconductor pellet is placed or set in a resin-molding package, through holes are provided in leads for the purpose of increasing the occupation area ratio of a resin portion. Furthermore, each of the leads corresponding to the lower surface of the pellet is branched into a plurality of portions in the widthwise direction thereof in order to reduce a stress. Further, in an insulating sheet which is interposed between the leads and the pellet, the dimension of the shorter lateral sides thereof is set smaller than that of the shorter lateral sides of the pellet in order to prevent cracks from occurring at the end part of the insulating sheet.
    Type: Grant
    Filed: June 12, 1990
    Date of Patent: January 22, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Toshihiro Yasuhara, Masachika Masuda, Asao Nishimura, Naozumi Hatada, Sueo Kawai, Makoto Kitano, Hideo Miura, Akihiro Yaguchi, Gen Murakami
  • Patent number: 4951120
    Abstract: A lead frame according this invention is structured such that the width or the length of the inner leads disposed adjacent to the tab suspending leads is made greater than that of other inner leads, whereby wires can be supported completely upon bonding to the leads and, accordingly, the bonding can be carried out surely and the occurrence of short-circuit of the wires can be prevented. Semiconductor devices of high electric reliability can be provided as a result these technics.
    Type: Grant
    Filed: December 13, 1988
    Date of Patent: August 21, 1990
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Yashuhisa Hagiwara, Masachika Masuda
  • Patent number: 4862246
    Abstract: Those portions (i.e., the inner lead portions) of the leads of a semiconductor device, which are sealed by a package, are formed with a plurality of depression in at least the surfaces and backs thereof such that the depressions have a smaller diameter at their bottoms than at their surfaces. As a result, both the adhesion strength between a sealer as the package and the inner lead portions of the leads and the mechanical strength of the leads are improved even in a semiconductor device having numerous leads. Moreover, the inner lead portions can be formed in their sides with a number of notches, which can be combined with those depressions to better improve the adhesion strength between the sealant and the inner lead portions of the leads and the mechanical strength of the leads.
    Type: Grant
    Filed: February 24, 1988
    Date of Patent: August 29, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Masachika Masuda, Akira Suzuki
  • Patent number: 4706105
    Abstract: A semiconductor device comprising a square package body, a plurality of leads which jut out from each of four sides of the package body, a beveled portion which is formed in at least one corner of the package body, and leads which jut out from the beveled portion.
    Type: Grant
    Filed: June 13, 1986
    Date of Patent: November 10, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Masachika Masuda, Gen Murakami