Abstract: Two semiconductor chips sealed with a mold resin are stacked on each other so that their backs are opposite to each other. The two semiconductor chips are supported by suspension leads fixedly secured to a circuit forming surface (lower surface) of the lower chip. A pair of bus bar leads is placed in the vicinity of the sides of these chips, and a plurality of leads are placed thereoutside. Wires are bonded between one surfaces of both the bus bar leads and the leads and one of the two semiconductor chips. Further, wires are bonded between the other surfaces of both the bus bar leads and the leads and the other of the semiconductor chips. Thus, a semiconductor device wherein the two semiconductor chips are laminated and sealed with a resin, is reduced in manufacturing cost, and the thinning of the present semiconductor device is pushed forward.

Abstract: A method is provided for forming a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form a depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.

Abstract: A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

Abstract: A semiconductor device comprising: a resin sealing body, plural semiconductor chips situated inside the resin sealing body and formed of rectangular-shaped plane surfaces, having a first main surface and second main surface facing each other, and having electrodes disposed on the first side of a first side and a second side of the first main surface, the first side and second side facing each other, and leads having inner parts situated inside the resin sealing body and outer parts situated outside the resin sealing body, the inner parts being electrically connected to the electrodes of the plural semiconductor chips via bonding wires, wherein: the first main surfaces are aligned in the same direction with their respective first sides situated on the same side, and the plural semiconductor chips are laminated in positions offset with respect to one another such that the electrodes of one of the mutually opposite semiconductor chips are situated further outside than the first sides of the other semiconductor c

Abstract: In a package of an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is disclosed a technique for thinning the package and speeding up signal transmission. Specifically, by partially reducing the thicknesses of the signal inner leads arranged over the major face of the semiconductor chip, the thickness of a sealing resin is reduced while ensuring the mechanical strength of the package. Moreover, the signal inner leads arranged over the major face of the semiconductor chip are arranged at predetermined spacings from the major face of the semiconductor chip. The power supplying inner leads are bonded to the major face of the semiconductor chip, thus providing a package having a reduced parasitic capacitance.

Abstract: A semiconductor device having power supply leads and signal leads on the main surface of a semiconductor chip. Since floating capacitance applied to the power supply leads can be made large and floating capacitance applied to the signal leads can be made small by making the interval between the signal leads and the semiconductor chip larger than the interval between the power supply leads and the semiconductor chip, the prevention of fluctuations in power source potential and the acceleration of the signal propagation speed can be carried out at the same time. As a result, the electric characteristics of the semiconductor device can be improved.

Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

Abstract: In a package of an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is disclosed a technique for thinning the package and speeding up signal transmission. Specifically, by partially reducing the thicknesses of the signal inner leads arranged over the major face of the semiconductor chip, the thickness of a sealing resin is reduced while ensuring the mechanical strength of the package. Moreover, the signal inner leads arranged over the major face of the semiconductor chip are arranged at predetermined spacings from the major face of the semiconductor chip. The power supplying inner leads are bonded to the major face of the semiconductor chip, thus providing a package having a reduced parasitic capacitance.

Abstract: The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.

Abstract: Two memory chips mounted over a base substrate have the same external size and have a flush memory of the same memory capacity formed thereon. These memory chips are mounted over the base substrate with one of them being overlapped with the upper portion of the other one and at the same time, they are stacked with their faces being turned in the same direction. The bonding pads BP of one of the memory chips are disposed in the vicinity of the bonding pads BP of the other memory chip. In addition, the upper memory chip is stacked over the lower memory chip in such a way that the upper memory chip is slid in a direction (X direction) parallel to the one side of the lower memory chip and in a direction (Y direction) perpendicular thereto in order to prevent partial overlapping of it with the bonding pads BP of the lower memory chip.

Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

Abstract: In a package of an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is disclosed a technique for thinning the package and speeding up signal transmission.

Abstract: A thin and highly reliable surface-mount-type package is provided for a semiconductor device.

Abstract: To realize low-profile electronic apparatus (a memory module and a memory card) of a large storage size by mounting tape carrier packages (TCPs) with a memory chip encapsulated onto a wiring board in high density. To be more specific, a TCP is composed of an insulating tape, leads formed on one side thereof, a potting resin with a semiconductor chip encapsulated, and a pair of support leads arranged on two opposite short sides. The pair of support leads function to hold the TCP at a constant tilt angle relative to the mounting surface of the wiring board. By varying the length vertical to the mounting surface, the TCP can be mounted to a desired tilt angle.

Abstract: In a package having an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is a technique for thinning the package and speeding up signal transmission. Specifically, by partially reducing the thicknesses of the signal inner leads arranged over the major face of the semiconductor chip, the thickness of a sealing resin is reduced while ensuring the mechanical strength of the package. Moreover, the signal inner leads arranged over the major face of the semiconductor chip are arranged at predetermined spacings from the major face of the semiconductor chip. The power supplying inner leads are bonded to the major face of the semiconductor chip, thus providing a package having a reduced parasitic capacitance.

Abstract: The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form a depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.

Abstract: Disclosed is a packaged semiconductor device, e.g., of the lead-on-chip type, having reduced thickness, by providing only an adhesive (without a base film) between inner lead portions of the leads and the semiconductor chip to adhere the inner-lead portions to the chip. The adhesive can cover a dicing area of the semiconductor chip, and, in general, can cover edge parts of the chip (and extend beyond the edge of the chip) to prevent short-circuits between the inner lead portions and the semiconductor chip. The outer lead portions have a lower outer end part and a part, closer to the package body, which extends upward obliquely; has stopper members on the obliquely extending part; and has an obliquely extending part with a greater width than a width of the outer end parts of the outer lead portions, to facilitate stacking of packaged semiconductor chips on each other, e.g., for mounting on a printed circuit board. Packaged semiconductor chips having, e.g.

Abstract: A semiconductor device in which inner leads among a plurality of leads are arranged on a circuit formation face of a semiconductor chip encapsulated by a resin encapsulating body and bonding pads formed on the circuit formation face of the chip and the inner leads are electrically connected. An adhesive is selectively applied only to the inner leads on the outermost sides arranged on both ends of the chip among the plurality of inner leads. The circuit formation face of the chip and the inner leads of the selected leads are joined with the adhesive Each of the selected leads has a step on the main face of the semiconductor chip and the leads except for the selected leads have almost straight shapes without being processed to have steps.

Abstract: Ends of inner leads are disposed in the vicinity of a peripheral end of a semiconductor chip and a portion of an insulating film tape is affixed to a main surface of the semiconductor chip by an adhesive while other portions of the insulating film tape are affixed to portions of the inner leads by an adhesive. Electrode pads provided in the main surface of the semiconductor chip are electrically connected to the ends of the corresponding inner leads by bonding wires, and the semiconductor chip, the inner leads, the electrode pads, the insulating film tape and the bonding wires are sealed by a resin molding. The thickness of the insulating film tape is smaller than a height from the main surface of the semiconductor chip to an apex of the bonding wire. Surfaces of the ends of the inner leads connected to the bonding wires are positioned lower than the main surface of the semiconductor chip and the inner leads are positioned between the main surface and an opposite surface of the semiconductor chip.

Abstract: An ultra-thin resin molded semiconductor device of high reliability with low cost and with easy repair at time of mounting. A plurality of these semiconductor devices are stacked to provide a semiconductor module which has a higher function than semiconductor devices in the same volume, and a card type module utilizing assembled by the stacked semiconductor module is provided. In manufacturing the semiconductor module, an extremely thin lead frame and an LSI chip are directly connected together, and the mirror surface of the LSI chip is exposed by using a low viscosity epoxy resin to have a thin molding. The mirror surface is grinded to have a further thin thickness of the whole structure of the semiconductor device. A part of the lead frame is formed as a reinforcing member, a heat radiation path, a light shielding part for shielding the LSI from harmful light beams, or a positioning base for mounting a substrate.