Patents by Inventor Masaharu Nagai
Masaharu Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11965817Abstract: Disclosed is a cell classification method, to be executed by an analyzer, for classifying cells contained in a specimen, including: preparing a first measurement sample by treating a specimen under a first preparation condition; obtaining a first signal from the prepared first measurement sample; classifying, by using the first signal, cells contained in the first measurement sample; preparing a second measurement sample by treating the specimen under a second preparation condition different from the first preparation condition; obtaining a second signal from the prepared second measurement sample; classifying, by using the second signal, cells contained in the second measurement sample; and comparing a result of the cell classification performed by using the first signal and a result of the cell classification performed by using the second signal, with each other, and outputting an analysis result including a number of cells on the basis of a result of the comparison.Type: GrantFiled: March 4, 2021Date of Patent: April 23, 2024Assignee: SYSMEX CORPORATIONInventors: Yuki Shida, Yukiko Nakamura, Ken Nishikawa, Kota Misawa, Hikaru Onoue, Takaaki Nagai, Masaki Abe, Takahito Mihara, Masaharu Shibata, Konobu Kimura
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Patent number: 10903402Abstract: An object of the present invention is to provide such a sealing structure that a material to be a deterioration factor such as water or oxygen is prevented from entering from external and sufficient reliability is obtained in a display using an organic or inorganic electroluminescent element. In view of the above object, focusing on permeability of an interlayer insulating film, deterioration of an electroluminescent element is suppressed and sufficient reliability is obtained by preventing water entry from an interlayer insulating film according to the present invention.Type: GrantFiled: July 25, 2019Date of Patent: January 26, 2021Inventors: Kaoru Tsuchiya, Aya Anzai, Masayuki Sakakura, Masaharu Nagai, Yutaka Matsuda
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Publication number: 20200020835Abstract: An object of the present invention is to provide such a sealing structure that a material to be a deterioration factor such as water or oxygen is prevented from entering from external and sufficient reliability is obtained in a display using an organic or inorganic electroluminescent element. In view of the above object, focusing on permeability of an interlayer insulating film, deterioration of an electroluminescent element is suppressed and sufficient reliability is obtained by preventing water entry from an interlayer insulating film according to the present invention.Type: ApplicationFiled: July 25, 2019Publication date: January 16, 2020Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kaoru TSUCHIYA, Aya ANZAI, Masayuki SAKAKURA, Masaharu NAGAI, Yutaka MATSUDA
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Patent number: 10367124Abstract: An object of the present invention is to provide such a sealing structure that a material to be a deterioration factor such as water or oxygen is prevented from entering from external and sufficient reliability is obtained in a display using an organic or inorganic electroluminescent element. In view of the above object, focusing on permeability of an interlayer insulating film, deterioration of an electroluminescent element is suppressed and sufficient reliability is obtained by preventing water entry from an interlayer insulating film according to the present invention.Type: GrantFiled: March 13, 2018Date of Patent: July 30, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kaoru Tsuchiya, Aya Anzai, Masayuki Sakakura, Masaharu Nagai, Yutaka Matsuda
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Patent number: 10141452Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer.Type: GrantFiled: January 8, 2018Date of Patent: November 27, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Daigo Ito, Daisuke Matsubayashi, Masaharu Nagai, Yoshiaki Yamamoto, Takashi Hamada, Yutaka Okazaki, Shinya Sasagawa, Motomu Kurata, Naoto Yamade
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Publication number: 20180204988Abstract: An object of the present invention is to provide such a sealing structure that a material to be a deterioration factor such as water or oxygen is prevented from entering from external and sufficient reliability is obtained in a display using an organic or inorganic electroluminescent element. In view of the above object, focusing on permeability of an interlayer insulating film, deterioration of an electroluminescent element is suppressed and sufficient reliability is obtained by preventing water entry from an interlayer insulating film according to the present invention.Type: ApplicationFiled: March 13, 2018Publication date: July 19, 2018Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kaoru Tsuchiya, Aya Anzai, Masayuki Sakakura, Masaharu Nagai, Yutaka Matsuda
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Publication number: 20180197997Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer.Type: ApplicationFiled: January 8, 2018Publication date: July 12, 2018Inventors: Daigo ITO, Daisuke Matsubayashi, Masaharu Nagai, Yoshiaki Yamamoto, Takashi Hamada, Yutaka Okazaki, Shinya Sasagawa, Motomu Kurata, Naoto Yamade
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Patent number: 9923127Abstract: An object of the present invention is to provide such a sealing structure that a material to be a deterioration factor such as water or oxygen is prevented from entering from external and sufficient reliability is obtained in a display using an organic or inorganic electroluminescent element. In view of the above object, focusing on permeability of an interlayer insulating film, deterioration of an electroluminescent element is suppressed and sufficient reliability is obtained by preventing water entry from an interlayer insulating film according to the present invention.Type: GrantFiled: May 9, 2014Date of Patent: March 20, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kaoru Tsuchiya, Aya Anzai, Masayuki Sakakura, Masaharu Nagai, Yutaka Matsuda
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Patent number: 9871145Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer.Type: GrantFiled: June 21, 2017Date of Patent: January 16, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Daigo Ito, Daisuke Matsubayashi, Masaharu Nagai, Yoshiaki Yamamoto, Takashi Hamada, Yutaka Okazaki, Shinya Sasagawa, Motomu Kurata, Naoto Yamade
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Publication number: 20170288064Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer.Type: ApplicationFiled: June 21, 2017Publication date: October 5, 2017Inventors: Daigo ITO, Daisuke MATSUBAYASHI, Masaharu NAGAI, Yoshiaki YAMAMOTO, Takashi HAMADA, Yutaka OKAZAKI, Shinya SASAGAWA, Motomu KURATA, Naoto YAMADE
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Patent number: 9691905Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer.Type: GrantFiled: June 15, 2016Date of Patent: June 27, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Daigo Ito, Daisuke Matsubayashi, Masaharu Nagai, Yoshiaki Yamamoto, Takashi Hamada, Yutaka Okazaki, Shinya Sasagawa, Motomu Kurata, Naoto Yamade
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Publication number: 20160372606Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer.Type: ApplicationFiled: June 15, 2016Publication date: December 22, 2016Inventors: Daigo ITO, Daisuke MATSUBAYASHI, Masaharu NAGAI, Yoshiaki YAMAMOTO, Takashi HAMADA, Yutaka OKAZAKI, Shinya SASAGAWA, Motomu KURATA, Naoto YAMADE
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Patent number: 9472656Abstract: A semiconductor device including a minute transistor with a short channel length is provided. A gate insulating layer is formed over a gate electrode layer; an oxide semiconductor layer is formed over the gate insulating layer; a first conductive layer and a second conductive layer are formed over the oxide semiconductor layer; a conductive film is formed over the first conductive layer and the second conductive layer; a resist mask is formed over the conductive film by performing electron beam exposure; and then a third conductive layer and a fourth conductive layer are formed over and in contact with the first conductive layer and the second conductive layer, respectively, by selectively etching the conductive film.Type: GrantFiled: August 27, 2015Date of Patent: October 18, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Atsuo Isobe, Yoshinori Ieda, Masaharu Nagai
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Publication number: 20150372123Abstract: A semiconductor device including a minute transistor with a short channel length is provided. A gate insulating layer is formed over a gate electrode layer; an oxide semiconductor layer is formed over the gate insulating layer; a first conductive layer and a second conductive layer are formed over the oxide semiconductor layer; a conductive film is formed over the first conductive layer and the second conductive layer; a resist mask is formed over the conductive film by performing electron beam exposure; and then a third conductive layer and a fourth conductive layer are formed over and in contact with the first conductive layer and the second conductive layer, respectively, by selectively etching the conductive film.Type: ApplicationFiled: August 27, 2015Publication date: December 24, 2015Inventors: Shunpei YAMAZAKI, Atsuo ISOBE, Yoshinori IEDA, Masaharu NAGAI
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Patent number: 9142679Abstract: A semiconductor device including a minute transistor with a short channel length is provided. A gate insulating layer is formed over a gate electrode layer; an oxide semiconductor layer is formed over the gate insulating layer; a first conductive layer and a second conductive layer are formed over the oxide semiconductor layer; a conductive film is formed over the first conductive layer and the second conductive layer; a resist mask is formed over the conductive film by performing electron beam exposure; and then a third conductive layer and a fourth conductive layer are formed over and in contact with the first conductive layer and the second conductive layer, respectively, by selectively etching the conductive film.Type: GrantFiled: November 27, 2012Date of Patent: September 22, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Atsuo Isobe, Yoshinori Ieda, Masaharu Nagai
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Publication number: 20140246694Abstract: An object of the present invention is to provide such a sealing structure that a material to be a deterioration factor such as water or oxygen is prevented from entering from external and sufficient reliability is obtained in a display using an organic or inorganic electroluminescent element. In view of the above object, focusing on permeability of an interlayer insulating film, deterioration of an electroluminescent element is suppressed and sufficient reliability is obtained by preventing water entry from an interlayer insulating film according to the present invention.Type: ApplicationFiled: May 9, 2014Publication date: September 4, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kaoru Tsuchiya, Aya ANZAI, Masayuki SAKAKURA, Masaharu NAGAI, Yutaka MATSUDA
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Patent number: 8723417Abstract: An object of the present invention is to provide such a sealing structure that a material to be a deterioration factor such as water or oxygen is prevented from entering from external and sufficient reliability is obtained in a display using an organic or inorganic electroluminescent element. In view of the above object, focusing on permeability of an interlayer insulating film, deterioration of an electroluminescent element is suppressed and sufficient reliability is obtained by preventing water entry from an interlayer insulating film according to the present invention.Type: GrantFiled: April 18, 2011Date of Patent: May 13, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kaoru Tsuchiya, Aya Anzai, Masayuki Sakakura, Masaharu Nagai, Yutaka Matsuda
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Patent number: 8486772Abstract: The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step.Type: GrantFiled: April 24, 2012Date of Patent: July 16, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuya Hanaoka, Hideki Tsuya, Masaharu Nagai
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Patent number: 8455873Abstract: It is an object of the present invention to provide a high reliable EL display device and a manufacturing method thereof by shielding intruding moisture or oxygen which is a factor of deteriorating the property of an EL element without enlarging the EL display device. In the invention, application is used as a method for forming a high thermostability planarizing film 16, typically, an interlayer insulating film (a film which serves as a base film of a light emitting element later) of a TFT in which a skeletal structure is configured by the combination of silicon (Si) and oxygen (O). After the formation, an edge portion or an opening portion is formed to have a tapered shape. Afterwards, distortion is given by adding an inert element with a comparatively large atomic radius to modify or highly densify a surface (including a side surface) for preventing the intrusion of moisture or oxygen.Type: GrantFiled: June 1, 2011Date of Patent: June 4, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Masaharu Nagai, Osamu Nakamura
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Patent number: 8426945Abstract: To provide a semiconductor device in which a channel formation region can be thinned without adversely affecting a source region and a drain region through a simple process and a method for manufacturing the semiconductor device. In the method for manufacturing a semiconductor device, a semiconductor film, having a thickness smaller than a height of a projection of a substrate, is formed over a surface of the substrate having the projections; the semiconductor film is etched to have an island shape with a resist used as a mask; the resist is etched to expose a portion of the semiconductor film which covers a top surface of the projection; and the exposed portion of the semiconductor film is etched to be thin, while the adjacent portions of the semiconductor film on both sides of the projection remain covered with the resist.Type: GrantFiled: September 6, 2011Date of Patent: April 23, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masaharu Nagai, Takafumi Mizoguchi