Patents by Inventor Masaharu Nagai

Masaharu Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070037070
    Abstract: The present invention provides a light exposure mask which can form a photoresist layer in a semi-transmissive portion with uniform thickness, and a method for manufacturing a semiconductor device in which the number of photolithography steps (the number of masks) necessary for manufacturing a TFT substrate is reduced by using the light exposure mask. A light exposure mask is used, which includes a transmissive portion, a light shielding portion, and a semi-transmissive portion having a light intensity reduction function where lines and spaces are repeatedly formed, wherein the sum of a line width L of a light shielding material and a space width S between light shielding materials in the semi-transmissive portion satisfies a conditional expression (2n/3)×m?L+S?(6n/5)×m when a resolution of a light exposure apparatus is represented by n and a projection magnification is represented by 1/m (m?1).
    Type: Application
    Filed: August 8, 2006
    Publication date: February 15, 2007
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hideto OHNUMA, Masaharu NAGAI
  • Publication number: 20060275710
    Abstract: To provide a semiconductor device having a circuit with high operating performance and high reliability, and improve the reliability of the semiconductor device, thereby improving the reliability of an electronic device having the same. The aforementioned object is achieved by combining a step of crystallizing a semiconductor layer by irradiation with continuous wave laser beams or pulsed laser beams with a repetition rate of 10 MHz or more, while scanning in one direction; a step of photolithography with the use of a photomask or a leticle including an auxiliary pattern which is formed of a diffraction grating pattern or a semi-transmissive film having a function of reducing the light intensity; and a step of performing oxidation, nitridation, or surface-modification to the surface of the semiconductor film, an insulating film, or a conductive film, with high-density plasma with a low electron temperature.
    Type: Application
    Filed: May 25, 2006
    Publication date: December 7, 2006
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsuya Kakehata, Hideto Ohnuma, Masaharu Nagai, Mitsuaki Osame, Masayuki Sakakura, Shigeki Komori
  • Publication number: 20060261336
    Abstract: It is an object of the present invention to form a plurality of elements in a limited area to reduce the area occupied by the elements for integration so that further higher resolution (increase in number of pixels), reduction of each display pixel pitch with miniaturization, and integration of a driver circuit that drives a pixel portion can be advanced in semiconductor devices such as liquid crystal display devices and light-emitting devices that has EL elements. A photomask or a reticle provided with an assist pattern that is composed of a diffraction grating pattern or a semi-transparent film and has a function of reducing a light intensity is applied to a photolithography process for forming a gate electrode to form a complicated gate electrode. In addition, a top-gate TFT that has the multi-gate structure described above and a top gate TFT that has a single-gate structure can be formed on the same substrate just by changing the mask without increasing the number of processes.
    Type: Application
    Filed: May 16, 2006
    Publication date: November 23, 2006
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hideto Ohnuma, Masaharu Nagai, Mitsuaki Osame, Masayuki Sakakura, Shigeki Komori, Shunpei Yamazaki
  • Publication number: 20050067953
    Abstract: An object of the present invention is to realize a light emitting device having low power consumption and high stability, in addition to improve extraction efficiency of light generated in a light emitting element. At least an interlayer insulating film (including a planarizing film), an anode, and a bank covering an edge portion of the anode contain-chemically and physically stable silicon oxide, or are made of a material containing silicon oxide as its main component in order to accomplish a light emitting device having high stability. Generation of heat in a light emitting panel can be suppressed in addition to increase in efficiency (luminance/current) of a light emitting panel according to the structure of the present invention. Consequently, synergistic effect on reliability of a light emitting device is obtained.
    Type: Application
    Filed: September 3, 2004
    Publication date: March 31, 2005
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Takashi Hamada, Masaharu Nagai, Yutaka Matsuda
  • Publication number: 20050062057
    Abstract: The present invention provides a highly stable light emitting device having high light-emitting efficiency (light-extraction efficiency) with high luminance and low power consumption, and a method of manufacturing thereof. A partition wall and a heat-resistant planarizing film are formed of a same material so as to be well-adhered to each other, thereby reducing material costs. Either an anode or a cathode is formed on the heat-resistant planarizing film. The partition wall and the heat-resistant planarizing film is adhered to each other without inserting a film having different refractive index therebetween, and therefore reflection of light is not caused in an interface.
    Type: Application
    Filed: September 16, 2004
    Publication date: March 24, 2005
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Masaharu Nagai, Yutaka Matsuda, Keiko Saito, Hisao Ikeda
  • Publication number: 20050062409
    Abstract: It is an object of the present invention to provide a reliable display device and a method for manufacturing the display device reducing the number of manufacturing steps, and with higher yield. A display device according to the invention includes a plurality of display elements each having a first electrode, a layer containing an organic compound, and a second electrode. The display device further includes a heat-resistant planarizing film over a substrate having an insulating surface, a first electrode over the heat-resistant planarizing film, a wiring covering an end portion of the first electrode, a partition wall covering the end portion of first electrode and the wiring, a layer containing an organic compound, and a second electrode over the layer containing an organic compound.
    Type: Application
    Filed: September 14, 2004
    Publication date: March 24, 2005
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Masaharu Nagai, Yutaka Matsuda, Kengo Akimoto, Gen Fujii, Tetsuji Yamaguchi
  • Publication number: 20050046346
    Abstract: An object of the present invention is to provide such a sealing structure that a material to be a deterioration factor such as water or oxygen is prevented from entering from external and sufficient reliability is obtained in a display using an organic or inorganic electroluminescent element. In view of the above object, focusing on permeability of an interlayer insulating film, deterioration of an electroluminescent element is suppressed and sufficient reliability is obtained by preventing water entry from an interlayer insulating film according to the present invention.
    Type: Application
    Filed: August 17, 2004
    Publication date: March 3, 2005
    Inventors: Kaoru Tsuchiya, Aya Anzai, Masayuki Sakakura, Masaharu Nagai, Yutaka Matsuda
  • Publication number: 20050045891
    Abstract: It is an object of the present invention to provide a high reliable EL display device and a manufacturing method thereof by shielding intruding moisture or oxygen which is a factor of deteriorating the property of an EL element without enlarging the EL display device. In the invention, application is used as a method for forming a high thermostability planarizing film 16, typically, an interlayer insulating film (a film which serves as a base film of a light emitting element later) of a TFT in which a skeletal structure is configured by the combination of silicon (Si) and oxygen (O). After the formation, an edge portion or an opening portion is formed to have a tapered shape. Afterwards, distortion is given by adding an inert element with a comparatively large atomic radius to modify or highly densify a surface (including a side surface) for preventing the intrusion of moisture or oxygen.
    Type: Application
    Filed: August 26, 2004
    Publication date: March 3, 2005
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masaharu Nagai, Osamu Nakamura
  • Publication number: 20040091820
    Abstract: It is an object to provide a technique for removing a resist favorably without leaving residue in the case of using a nonaqueous resist stripper. According to the present invention, in order to achieve the object, when a resist pattern is removed by using the nonaqueous resist stripper, it becomes easier to remove the resist pattern after dry etching or ion doping, by performing exposure treatment on the resist pattern. After a resist pattern is formed from a DNQ-novolac resin type of positive resist composition, the resist pattern is irradiated with light within the range of photosensitive wavelength of the DNQ photosensitizer, thereby removing the resist pattern with the nonaqueous resist stripper.
    Type: Application
    Filed: October 29, 2003
    Publication date: May 13, 2004
    Inventors: Masaharu Nagai, Kiyofumi Ogino, Teruhisa Nakai, Eiji Shioda
  • Publication number: 20030228740
    Abstract: In a resist pattern forming method in which bake processing is performed at a temperature not lower than a glass transition temperature in order to obtain the desired sidewall angle, resist removable is difficult. Accordingly, in the resist pattern forming method of performing bake processing at a temperature not lower than a glass transition temperature, a process margin for resist removability cannot be ensured, so that there is the problem that it is impossible to compatibly realize both the formation of a resist pattern having the desired sidewall angle and the resist removability of the resist pattern. The invention aims to solve the problem. A resist pattern including a diazonaphthoquinone (DNQ)-novolac resin type of positive resist is formed, and the resist pattern is irradiated with light within the range of photosensitive wavelengths of a DNQ photosensitizer to perform bake processing on the resist pattern at a temperature not lower than the glass transition temperature of the resist pattern.
    Type: Application
    Filed: April 3, 2003
    Publication date: December 11, 2003
    Inventors: Masaharu Nagai, Ichiro Uehara
  • Patent number: 6456639
    Abstract: The invention provides a semiconductor light emitting device whose operating voltage can be easily reduced, a method of producing the same, and an optical device. An n-type clad layer, a first guide layer, an active layer, a second guide layer, a p-type clad layer, a first semiconductor layer, and a second semiconductor layer of ZnSe are successively grown on an n-type substrate. An alkali compound layer of Na2Se is then formed thereon. Subsequently, a heat treatment is performed by means of irradiation of an excimer laser beam so that at least a part of the second semiconductor layer and at least a part of the alkali compound layer are altered thereby forming a contact layer. Furthermore, a p-side electrode is formed on the contact layer. The contact layer contains an alkali metal serving as a p-type impurity so that the contact layer has a low electric resistance thereby achieving a reduction in the operating voltage and thus a reduction in the operating power.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: September 24, 2002
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Yoshinori Hatanaka, Toru Aoki, Masaharu Nagai
  • Patent number: 6414975
    Abstract: The invention provides a semiconductor light emitting device whose operating voltage can be easily reduced, a method of producing the same, and an optical device. An n-type clad layer, a first guide layer, an active layer, a second guide layer, a p-type clad layer, a first semiconductor layer, and a second semiconductor layer of ZnSe are successively grown on an n-type substrate. An alkali compound layer of Na2Se is then formed thereon. Subsequently, a heat treatment is performed by means of irradiation of an excimer laser beam so that at least a part of the second semiconductor layer and at least a part of the alkali compound layer are altered thereby forming a contact layer. Furthermore, a p-side electrode is formed on the contact layer. The contact layer contains an alkali metal serving as a p-type impurity so that the contact layer has a low electric resistance thereby achieving a reduction in the operating voltage and thus a reduction in the operating power.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: July 2, 2002
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Yoshinori Hatanaka, Toru Aoki, Masaharu Nagai
  • Publication number: 20010028666
    Abstract: The invention provides a semiconductor light emitting device whose operating voltage can be easily reduced, a method of producing the same, and an optical device. An n-type clad layer, a first guide layer, an active layer, a second guide layer, a p-type clad layer, a first semiconductor layer, and a second semiconductor layer of ZnSe are successively grown on an n-type substrate. An alkali compound layer of Na2Se is then formed thereon. Subsequently, a heat treatment is performed by means of irradiation of an excimer laser beam so that at least a part of the second semiconductor layer and at least a part of the alkali compound layer are altered thereby forming a contact layer. Furthermore, a p-side electrode is formed on the contact layer. The contact layer contains an alkali metal serving as a p-type impurity so that the contact layer has a low electric resistance thereby achieving a reduction in the operating voltage and thus a reduction in the operating power.
    Type: Application
    Filed: May 24, 2001
    Publication date: October 11, 2001
    Applicant: Sony Corporation
    Inventors: Akira Ishibashi, Yoshinori Hatanaka, Toru Aoki, Masaharu Nagai
  • Patent number: 6069020
    Abstract: In a method of manufacturing a semiconductor light-emitting device composed of a II-VI compound semiconductor in which at least more than one kind of elements of Zn, Be, Mg, Cd or Hg are used as a II-group element and at least more than one kind of elements of Se, S, Te are used as a VI-group element and which includes first conductivity type and second conductivity type cladding layers and an active layer, a supply ratio VI/II ratio of VI-group element and II-group element required when the active layer is epitaxially deposited is selected to be greater than 1.1 and the active layer is deposited epitaxially. Thus, there may be obtained a highly-reliable semiconductor light-emitting device whose life time is made longer.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: May 30, 2000
    Assignee: Sony Corporation
    Inventors: Eisaku Kato, Hiroyasu Noguchi, Masaharu Nagai
  • Patent number: 6024794
    Abstract: By applying the method, the critical film thickness of a compound semiconductor layer is determined, and a semiconductor device having a compound semiconductor layer with an optimized film thickness excellent in emitting performance is manufactured.The relationship between film thickness of a compound semiconductor layer and photoluminescence (PL) corresponding to the film thickness is obtained by measurement, the film thickness where PL exhibits a peak is designated as critical film thickness. The semiconductor layer comprises II-VI group compound semiconductor layer containing at least cadmium. The relationship between the critical film thickness and cadmium composition ratio is obtained by measurement. An equation which approximates the relationship between the critical film thickness and cadmium composition ratio is formulated.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: February 15, 2000
    Assignee: Sony Corporation
    Inventors: Koshi Tamamura, Hironori Tsukamoto, Masaharu Nagai
  • Patent number: 6020601
    Abstract: A semiconductor light-emitting device longer in life time and higher in reliability is provided which is formed of, on a substrate (1), a first conductivity type cladding layer (3) and a second conductivity type cladding layer (7) made of Zn.sub.x Mg.sub.Y Be.sub.1-x-y S.sub.Z Se.sub.1-z (0<x<1,0<y<1,0.ltoreq.z<1) system compound semiconductor, at least one active layer (5) made of Zn.sub.A Cd.sub.B Be.sub.1-A-B S.sub.c Se.sub.1-C (0<A.ltoreq.1, 0.ltoreq.B<1, 0.ltoreq.C<1), having a compressive distortion relative to the above substrate and located between the first and second conductivity type cladding layers, and at least one strain compensation layer having a tensile distortion relative to the above substrate and made of Zn.sub.u Cd.sub.1-u S.sub.v Se.sub.1-v (0<u.ltoreq.1, 0.ltoreq.v<1).
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: February 1, 2000
    Assignee: Sony Corporation
    Inventors: Hiroyasu Noguchi, Eisaku Kato, Masaharu Nagai
  • Patent number: 5865897
    Abstract: A film of a II-VI group compound semiconductor of at least one of elements belonging to the II group of the periodic table and at least one of elements belonging to the VI group of the periodic table is deposited on a substrate. When the film is deposited on the substrate, a plasma of nitrogen in an excited state is applied to the substrate while removing charged particles from said plasma by a charged particle removing means. The deposited film of a nitrogen-doped II-VI group compound semiconductor has an increased percentage of activated nitrogen atoms and improved crystallinity.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: February 2, 1999
    Assignee: Sony Corporation
    Inventors: Satoshi Ito, Satoshi Taniguchi, Masao Ikeda, Hiroyuki Okuyama, Hironori Tsukamoto, Masaharu Nagai, Koshi Tamamura
  • Patent number: 5828086
    Abstract: A semiconductor light emitting device ccomprises a first cladding layer, an active layer and a second cladding layer which are stacked on a semiconductor substrate. At least a part of the first cladding layer and the second cladding layer has a superlattice structure comprising II-VI compound semiconductor. Another semiconductor light emitting device comprises a first cladding layer, a first guide layer, an active layer, a second guide layer and a second cladding layer which are stacked on a semiconductor substrate. At least a part of the first cladding layer, the first guide layer, the second cladding layer and the second guide layer has a superlattice structure. Still anothr semiconductor light emitting device comprises a defect decomposing layer, a defect blocking layer, a first cladding layer, an active layer, a second cladding layer which are stacked on a semiconductor substrate. The defect decomposing layer and the defect blocking layer comprise a superlattice structure.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: October 27, 1998
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Satoshi Matsumoto, Masaharu Nagai, Satoshi Ito, Shigetaka Tomiya, Kazushi Nakano, Etsuo Morita
  • Patent number: 5695556
    Abstract: By applying the method, the critical film thickness of a compound semiconductor layer is determined, and a semiconductor device having a compound semiconductor layer with an optimized film thickness excellent in emitting performance is manufactured.The relationship between film thickness of a compound semiconductor layer and photoluminescence (PL) corresponding to the film thickness is obtained by measurement, the film thickness where PL exhibits a peak is designated as critical film thickness. The semiconductor layer comprises II-VI group compound semiconductor layer containing at least cadmium. The relationship between the critical film thickness and cadmium composition ratio is obtained by measurement. An equation which approximates the relationship between the critical film thickness and cadmium composition ratio is formulated.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: December 9, 1997
    Assignee: Sony Corporation
    Inventors: Koshi Tamamura, Hironori Tsukamoto, Masaharu Nagai, Masao Ikeda
  • Patent number: 5665977
    Abstract: A semiconductor light emitting device comprises a first cladding layer, an active layer and a second cladding layer which are stacked on a semiconductor substrate. At least a part of the first cladding layer and the second cladding layer has a superlattice structure comprising II-VI compound semiconductor. Another semiconductor light emitting device comprises a first cladding layer, a first guide layer, an active layer, a second guide layer and a second cladding layer which are stacked on semiconductor substrate. At least a part of the first cladding layer, the first guide layer, the second cladding layer and the second guide layer has a superlattice structure. Still another semiconductor light emitting device comprises a defect decomposing layer, a defect blocking layer, first cladding layer, an active layer, a second cladding layer which are stacked on a semiconductor substrate. The defect decomposing layer and the defect blocking layer comprise a superlattice structure.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: September 9, 1997
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Satoshi Matsumoto, Masaharu Nagai, Satoshi Ito, Shigetaka Tomiya, Kazushi Nakano, Etsuo Morita