Patents by Inventor Masaharu Nagai
Masaharu Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7829432Abstract: To improve bonding strength and improve reliability of an SOI substrate in bonding a semiconductor substrate and a base substrate to each other even when an insulating film containing nitrogen is used as a bonding layer, an oxide film is provided on the semiconductor substrate side, a nitrogen-containing layer is provided on the base substrate side, and the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate are bonded to each other. Further, plasma treatment is performed on at least one of the oxide film and the nitrogen-containing layer before bonding the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate to each other. Plasma treatment can be performed in a state in which a bias voltage is applied.Type: GrantFiled: June 23, 2009Date of Patent: November 9, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Kenichiro Makino, Yoichi Iikubo, Masaharu Nagai, Aiko Shiga
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Publication number: 20100273310Abstract: The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step.Type: ApplicationFiled: April 19, 2010Publication date: October 28, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kazuya HANAOKA, Hideki TSUYA, Masaharu NAGAI
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Patent number: 7816863Abstract: An object of the present invention is to realize a light emitting device having low power consumption and high stability, in addition to improve extraction efficiency of light generated in a light emitting element. At least an interlayer insulating film (including a planarizing film), an anode, and a bank covering an edge portion of the anode contain-chemically and physically stable silicon oxide, or are made of a material containing silicon oxide as its main component in order to accomplish a light emitting device having high stability. Generation of heat in a light emitting panel can be suppressed in addition to increase in efficiency (luminance/current) of a light emitting panel according to the structure of the present invention. Consequently, synergistic effect on reliability of a light emitting device is obtained.Type: GrantFiled: September 3, 2004Date of Patent: October 19, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Junichiro Sakata, Takashi Hamada, Masaharu Nagai, Yutaka Matsuda
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Patent number: 7799515Abstract: In a resist pattern forming method in which bake processing is performed at a temperature not lower than a glass transition temperature in order to obtain the desired sidewall angle, resist removable is difficult. Accordingly, in the resist pattern forming method of performing bake processing at a temperature not lower than a glass transition temperature, a process margin for resist removability cannot be ensured, so that there is the problem that it is impossible to compatibly realize both the formation of a resist pattern having the desired sidewall angle and the resist removability of the resist pattern. The invention aims to solve the problem. A resist pattern including a diazonaphthoquinone (DNQ)-novolac resin type of positive resist is formed, and the resist pattern is irradiated with light within the range of photosensitive wavelengths of a DNQ photosensitizer to perform bake processing on the resist pattern at a temperature not lower than the glass transition temperature of the resist pattern.Type: GrantFiled: January 18, 2008Date of Patent: September 21, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masaharu Nagai, Ichiro Uehara
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Patent number: 7737449Abstract: The present invention provides a highly stable light emitting device having high light-emitting efficiency (light-extraction efficiency) with high luminance and low power consumption, and a method of manufacturing thereof. A partition wall and a heat-resistant planarizing film are formed of a same material so as to be well-adhered to each other, thereby reducing material costs. Either an anode or a cathode is formed on the heat-resistant planarizing film. The partition wall and the heat-resistant planarizing film is adhered to each other without inserting a film having different refractive index therebetween, and therefore reflection of light is not caused in an interface.Type: GrantFiled: November 19, 2007Date of Patent: June 15, 2010Assignee: Semiconductor Energy Laboratory Co., LtdInventors: Shunpei Yamazaki, Masayuki Sakakura, Masaharu Nagai, Yutaka Matsuda, Keiko Saito, Hisao Ikeda
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Publication number: 20090325363Abstract: To improve bonding strength and improve reliability of an SOI substrate in bonding a semiconductor substrate and a base substrate to each other even when an insulating film containing nitrogen is used as a bonding layer, an oxide film is provided on the semiconductor substrate side, a nitrogen-containing layer is provided on the base substrate side, and the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate are bonded to each other. Further, plasma treatment is performed on at least one of the oxide film and the nitrogen-containing layer before bonding the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate to each other. Plasma treatment can be performed in a state in which a bias voltage is applied.Type: ApplicationFiled: June 23, 2009Publication date: December 31, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hideto OHNUMA, Kenichiro MAKINO, Yoichi IIKUBO, Masaharu NAGAI, Aiko SHIGA
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Publication number: 20090291536Abstract: It is an object of the present invention to form a plurality of elements in a limited area to reduce the area occupied by the elements for integration so that further higher resolution (increase in number of pixels), reduction of each display pixel pitch with miniaturization, and integration of a driver circuit that drives a pixel portion can be advanced in semiconductor devices such as liquid crystal display devices and light-emitting devices that has EL elements. A photomask or a reticle provided with an assist pattern that is composed of a diffraction grating pattern or a semi-transparent film and has a function of reducing a light intensity is applied to a photolithography process for forming a gate electrode to form a complicated gate electrode. In addition, a top-gate TFT that has the multi-gate structure described above and a top gate TFT that has a single-gate structure can be formed on the same substrate just by changing the mask without increasing the number of processes.Type: ApplicationFiled: August 3, 2009Publication date: November 26, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hideto Ohnuma, Masaharu Nagai, Mitsuaki Osame, Masayuki Sakakura, Shigeki Komori, Shunpei Yamazaki
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Patent number: 7608490Abstract: To provide a semiconductor device having a circuit with high operating performance and high reliability, and improve the reliability of the semiconductor device, thereby improving the reliability of an electronic device having the same. The aforementioned object is achieved by combining a step of crystallizing a semiconductor layer by irradiation with continuous wave laser beams or pulsed laser beams with a repetition rate of 10 MHz or more, while scanning in one direction; a step of photolithography with the use of a photomask or a leticle including an auxiliary pattern which is formed of a diffraction grating pattern or a semi-transmissive film having a function of reducing the light intensity; and a step of performing oxidation, nitridation, or surface-modification to the surface of the semiconductor film, an insulating film, or a conductive film, with high-density plasma with a low electron temperature.Type: GrantFiled: May 25, 2006Date of Patent: October 27, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Tetsuya Kakehata, Hideto Ohnuma, Masaharu Nagai, Mitsuaki Osame, Masayuki Sakakura, Shigeki Komori
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Patent number: 7579220Abstract: It is an object of the present invention to form a plurality of elements in a limited area to reduce the area occupied by the elements for integration so that further higher resolution (increase in number of pixels), reduction of each display pixel pitch with miniaturization, and integration of a driver circuit that drives a pixel portion can be advanced in semiconductor devices such as liquid crystal display devices and light-emitting devices that has EL elements. A photomask or a reticle provided with an assist pattern that is composed of a diffraction grating pattern or a semi-transparent film and has a function of reducing a light intensity is applied to a photolithography process for forming a gate electrode to form a complicated gate electrode. In addition, a top-gate TFT that has the multi-gate structure described above and a top gate TFT that has a single-gate structure can be formed on the same substrate just by changing the mask without increasing the number of processes.Type: GrantFiled: May 16, 2006Date of Patent: August 25, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Masaharu Nagai, Mitsuaki Osame, Masayuki Sakakura, Shigeki Komori, Shunpei Yamazaki
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Publication number: 20090195154Abstract: It is an object of the present invention to provide a reliable display device and a method for manufacturing the display device reducing the number of manufacturing steps, and with higher yield. A display device according to the invention includes a plurality of display elements each having a first electrode, a layer containing an organic compound, and a second electrode. The display device further includes a heat-resistant planarizing film over a substrate having an insulating surface, a first electrode over the heat-resistant planarizing film, a wiring covering an end portion of the first electrode, a partition wall covering the end portion of first electrode and the wiring, a layer containing an organic compound, and a second electrode over the layer containing an organic compound.Type: ApplicationFiled: March 18, 2009Publication date: August 6, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Masaharu NAGAI, Yutaka MATSUDA, Kengo AKIMOTO, Gen FUJII, Tetsuji YAMAGUCHI
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Patent number: 7520790Abstract: It is an object of the present invention to provide a reliable display device and a method for manufacturing the display device reducing the number of manufacturing steps, and with higher yield. A display device according to the invention includes a plurality of display elements each having a first electrode, a layer containing an organic compound, and a second electrode. The display device further includes a heat-resistant planarizing film over a substrate having an insulating surface, a first electrode over the heat-resistant planarizing film, a wiring covering an end portion of the first electrode, a partition wall covering the end portion of first electrode and the wiring, a layer containing an organic compound, and a second electrode over the layer containing an organic compound.Type: GrantFiled: September 14, 2004Date of Patent: April 21, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Masayuki Sakakura, Masaharu Nagai, Yutaka Matsuda, Kengo Akimoto, Gen Fujii, Tetsuji Yamaguchi
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Publication number: 20090051286Abstract: It is an object of the present invention to provide a high reliable EL display device and a manufacturing method thereof by shielding intruding moisture or oxygen which is a factor of deteriorating the property of an EL element without enlarging the EL display device. In the invention, application is used as a method for forming a high thermostability planarizing film 16, typically, an interlayer insulating film (a film which serves as a base film of a light emitting element later) of a TFT in which a skeletal structure is configured by the combination of silicon (Si) and oxygen (O). After the formation, an edge portion or an opening portion is formed to have a tapered shape. Afterwards, distortion is given by adding an inert element with a comparatively large atomic radius to modify or highly densify a surface (including a side surface) for preventing the intrusion of moisture or oxygen.Type: ApplicationFiled: October 15, 2008Publication date: February 26, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Masaharu NAGAI, Osamu NAKAMURA
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Publication number: 20090001467Abstract: To provide a semiconductor device in which a channel formation region can be thinned without adversely affecting a source region and a drain region through a simple process and a method for manufacturing the semiconductor device. In the method for manufacturing a semiconductor device, a semiconductor film, having a thickness smaller than a height of a projection of a substrate, is formed over a surface of the substrate having the projections; the semiconductor film is etched to have an island shape with a resist used as a mask; the resist is etched to expose a portion of the semiconductor film which covers a top surface of the projection; and the exposed portion of the semiconductor film is etched to be thin, while the adjacent portions of the semiconductor film on both sides of the projection remain covered with the resist.Type: ApplicationFiled: June 27, 2008Publication date: January 1, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Masaharu NAGAI, Takafumi MIZOGUCHI
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Patent number: 7465593Abstract: It is an object of the present invention to provide a high reliable EL display device and a manufacturing method thereof by shielding intruding moisture or oxygen which is a factor of deteriorating the property of an EL element without enlarging the EL display device. In the invention, application is used as a method for forming a high thermostability planarizing film 16, typically, an interlayer insulating film (a film which serves as a base film of a light emitting element later) of a TFT in which a skeletal structure is configured by the combination of silicon (Si) and oxygen (O). After the formation, an edge portion or an opening portion is formed to have a tapered shape. Afterwards, distortion is given by adding an inert element with a comparatively large atomic radius to modify or highly densify a surface (including a side surface) for preventing the intrusion of moisture or oxygen.Type: GrantFiled: January 9, 2008Date of Patent: December 16, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Masaharu Nagai, Osamu Nakamura
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Patent number: 7446336Abstract: It is an object of the present invention to provide a high reliable EL display device and a manufacturing method thereof by shielding intruding moisture or oxygen which is a factor of deteriorating the property of an EL element without enlarging the EL display device. In the invention, application is used as a method for forming a high thermostability planarizing film 16, typically, an interlayer insulating film (a film which serves as a base film of a light emitting element later) of a TFT in which a skeletal structure is configured by the combination of silicon (Si) and oxygen (O). After the formation, an edge portion or an opening portion is formed to have a tapered shape. Afterwards, distortion is given by adding an inert element with a comparatively large atomic radius to modify or highly densify a surface (including a side surface) for preventing the intrusion of moisture or oxygen.Type: GrantFiled: August 26, 2004Date of Patent: November 4, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Masaharu Nagai, Osamu Nakamura
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Publication number: 20080182209Abstract: In a resist pattern forming method in which bake processing is performed at a temperature not lower than a glass transition temperature in order to obtain the desired sidewall angle, resist removable is difficult. Accordingly, in the resist pattern forming method of performing bake processing at a temperature not lower than a glass transition temperature, a process margin for resist removability cannot be ensured, so that there is the problem that it is impossible to compatibly realize both the formation of a resist pattern having the desired sidewall angle and the resist removability of the resist pattern. The invention aims to solve the problem. A resist pattern including a diazonaphthoquinone (DNQ)-novolac resin type of positive resist is formed, and the resist pattern is irradiated with light within the range of photosensitive wavelengths of a DNQ photosensitizer to perform bake processing on the resist pattern at a temperature not lower than the glass transition temperature of the resist pattern.Type: ApplicationFiled: January 18, 2008Publication date: July 31, 2008Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Masaharu Nagai, Ichiro Uehara
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Publication number: 20080124848Abstract: It is an object of the present invention to provide a high reliable EL display device and a manufacturing method thereof by shielding intruding moisture or oxygen which is a factor of deteriorating the property of an EL element without enlarging the EL display device. In the invention, application is used as a method for forming a high thermostability planarizing film 16, typically, an interlayer insulating film (a film which serves as a base film of a light emitting element later) of a TFT in which a skeletal structure is configured by the combination of silicon (Si) and oxygen (O). After the formation, an edge portion or an opening portion is formed to have a tapered shape. Afterwards, distortion is given by adding an inert element with a comparatively large atomic radius to modify or highly densify a surface (including a side surface) for preventing the intrusion of moisture or oxygen.Type: ApplicationFiled: January 9, 2008Publication date: May 29, 2008Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Masaharu Nagai, Osamu Nakamura
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Publication number: 20080088245Abstract: The present invention provides a highly stable light emitting device having high light-emitting efficiency (light-extraction efficiency) with high luminance and low power consumption, and a method of manufacturing thereof. A partition wall and a heat-resistant planarizing film are formed of a same material so as to be well-adhered to each other, thereby reducing material costs. Either an anode or a cathode is formed on the heat-resistant planarizing film. The partition wall and the heat-resistant planarizing film is adhered to each other without inserting a film having different refractive index therebetween, and therefore reflection of light is not caused in an interface.Type: ApplicationFiled: November 19, 2007Publication date: April 17, 2008Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Masayuki Sakakura, Masaharu Nagai, Yutaka Matsuda, Keiko Saito, Hisao Ikeda
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Patent number: 7344825Abstract: In a resist pattern forming method in which bake processing is performed at a temperature not lower than a glass transition temperature in order to obtain the desired sidewall angle, resist removable is difficult. Accordingly, in the resist pattern forming method of performing bake processing at a temperature not lower than a glass transition temperature, a process margin for resist removability cannot be ensured, so that there is the problem that it is impossible to compatibly realize both the formation of a resist pattern having the desired sidewall angle and the resist removability of the resist pattern. The invention aims to solve the problem. A resist pattern including a diazonaphthoquinone (DNQ)-novolac resin type of positive resist is formed, and the resist pattern is irradiated with light within the range of photosensitive wavelengths of a DNQ photosensitizer to perform bake processing on the resist pattern at a temperature not lower than the glass transition temperature of the resist pattern.Type: GrantFiled: April 3, 2003Date of Patent: March 18, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masaharu Nagai, Ichiro Uehara
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Patent number: 7306978Abstract: The present invention provides a highly stable light emitting device having high light-emitting efficiency (light-extraction efficiency) with high luminance and low power consumption, and a method of manufacturing thereof. A partition wall and a heat-resistant planarizing film are formed of a same material so as to be well-adhered to each other, thereby reducing material costs. Either an anode or a cathode is formed on the heat-resistant planarizing film. The partition wall and the heat-resistant planarizing film is adhered to each other without inserting a film having different refractive index therebetween, and therefore reflection of light is not caused in an interface.Type: GrantFiled: September 16, 2004Date of Patent: December 11, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Masayuki Sakakura, Masaharu Nagai, Yutaka Matsuda, Keiko Saito, Hisao Ikeda