Patents by Inventor Masahiko Higashi

Masahiko Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8669161
    Abstract: A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: March 11, 2014
    Assignee: Spansion LLC
    Inventor: Masahiko Higashi
  • Publication number: 20140021529
    Abstract: A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated.
    Type: Application
    Filed: October 22, 2012
    Publication date: January 23, 2014
    Inventors: Naofumi TAKAHATA, Masahiko HIGASHI, Yukihiro UTSUNO
  • Publication number: 20140002438
    Abstract: An improved source driver of a liquid crystal display device. Upon detection of discontinuation of the supply of internal logic power to a logic processing unit, an alternative signal of a predetermined potential is generated. This alternative signal is supplied to a liquid crystal panel in place of an LCD drive signal. The logic processing unit is a device for processing an input image signal.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 2, 2014
    Inventors: Masahiko HIGASHI, Akira NAKAYAMA
  • Patent number: 8610199
    Abstract: A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 17, 2013
    Assignee: Spansion LLC
    Inventor: Masahiko Higashi
  • Patent number: 8404549
    Abstract: A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: March 26, 2013
    Assignee: Spansion LLC
    Inventor: Masahiko Higashi
  • Publication number: 20130020673
    Abstract: A protection diode includes a semiconductor substrate having a first region, a second region surrounding the first region, and a third region surrounding the second region; a first insulation layer disposed between the second region and the third region; a first conductive type semiconductor portion disposed in the third region; a second conductive type semiconductor portion disposed in the second region; and a capacity reduction layer disposed in the first region.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 24, 2013
    Inventors: Atsushi HIRAMA, Masahiko Higashi
  • Publication number: 20120315564
    Abstract: A composite body includes a substrate containing Cr; and a first composite oxide layer disposed on at least a part of a surface of the substrate, the first composite oxide layer having a spinel type crystal structure, a first largest content and a second largest content among constituent elements excluding oxygen of the first composite oxide layer being Zn and Al in random order. Accordingly, the composite body can suppress diffusion of Cr from the substrate containing Cr to the first composite oxide layer, and has improved long-term reliability. A collector member and a gas tank, each of which is formed of the composite body, can have improved long-term reliability. A fuel cell device having excellent long-term reliability can be obtained using the collector member and the gas tank.
    Type: Application
    Filed: February 25, 2011
    Publication date: December 13, 2012
    Applicant: KYOCERA CORPORATION
    Inventors: Tetsuro Fujimoto, Masahiko Higashi
  • Patent number: 8304914
    Abstract: A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: November 6, 2012
    Assignee: Spansion, LLC
    Inventors: Naofumi Takahata, Masahiko Higashi, Yukihiro Utsuno
  • Patent number: 8278171
    Abstract: There are provided a semiconductor device and a fabrication method therefor including an ONO film (18) formed on a semiconductor substrate (10), a word line (24) formed on the ONO film (18), a bit line (20) formed in the semiconductor substrate (10), and a conductive layer (32) that is in contact with the bit line (20), runs in a length direction of the bit line (20), and includes a polysilicon layer or a metal layer. In accordance with the present invention, a semiconductor device and a fabrication method therefor are provided wherein degradation of the writing and erasing characteristics and degradation of the transistor characteristics such as a junction leakage are suppressed, and the bit line resistance is decreased.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: October 2, 2012
    Assignee: Spansion LLC
    Inventors: Kenichi Fujii, Masahiko Higashi
  • Publication number: 20120181600
    Abstract: A semiconductor device fabricated by forming a dummy layer on a semiconductor substrate, forming a groove in the semiconductor substrate while using the dummy layer as a mask, forming a tunnel insulating film and a trap layer to cover an inner surface of the groove and the dummy layer, eliminating the trap layer formed above the upper surface and at the sides of the dummy layer, and forming a top insulating film to cover a remaining trap layer and the exposed tunnel insulating film.
    Type: Application
    Filed: October 18, 2011
    Publication date: July 19, 2012
    Inventor: Masahiko HIGASHI
  • Patent number: 8076206
    Abstract: A method for manufacturing a semiconductor device which includes steps of forming a dummy layer on a semiconductor substrate, forming a groove 12 in the semiconductor substrate while using the dummy layer as a mask, forming a tunnel insulating film and a trap layer to cover an inner surface of the groove and the dummy layer, eliminating the trap layer formed above the upper surface and at the sides of the dummy layer, and forming a top insulating film to cover a remaining trap layer and the exposed tunnel insulating film.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: December 13, 2011
    Assignee: Spansion LLC
    Inventor: Masahiko Higashi
  • Publication number: 20110281194
    Abstract: A heat-resistant alloy capable of effectively suppressing diffusion of Cr, as well as an alloy member for a fuel cell, a fuel cell stack device, a fuel cell module and a fuel cell device are provided. A heat-resistant alloy includes a Cr-containing alloy, and a Cr-diffusion suppression layer located on at least a part of a surface of the Cr-containing alloy, the Cr-diffusion suppression layer being made by laminating a first layer that contains a Zn-containing oxide and a second layer that does not contain ZnO but contains an (La, Sr)MnO3-based perovskite oxide in that order, so that it is possible to effectively suppress diffusion of Cr. By using the heat-resistant alloy for an alloy member for a fuel cell, a fuel cell stack device, a fuel cell module and a fuel cell device each having improved reliability can be obtained.
    Type: Application
    Filed: January 25, 2010
    Publication date: November 17, 2011
    Applicant: KYOCERA CORPORATION
    Inventors: Masahiko Higashi, Tetsurou Fujimoto, Norimitsu Fukami, Kenji Shimazu
  • Publication number: 20110183510
    Abstract: There are provided a semiconductor device and a fabrication method therefor including an ONO film (18) formed on a semiconductor substrate (10), a word line (24) formed on the ONO film (18), a bit line (20) formed in the semiconductor substrate (10), and a conductive layer (32) that is in contact with the bit line (20), runs in a length direction of the bit line (20), and includes a polysilicon layer or a metal layer. In accordance with the present invention, a semiconductor device and a fabrication method therefor are provided wherein degradation of the writing and erasing characteristics and degradation of the transistor characteristics such as a junction leakage are suppressed, and the bit line resistance is decreased.
    Type: Application
    Filed: April 7, 2011
    Publication date: July 28, 2011
    Inventors: Kenichi FUJII, Masahiko HIGASHI
  • Patent number: 7977189
    Abstract: The present invention relates to a semiconductor device that includes a semiconductor substrate (10) having source/drain diffusion regions (14) formed therein and control gates (20) formed thereon, with grooves (18) being formed on the surface of the semiconductor substrate (10) and being located below the control gates (20) and between the source/drain diffusion regions (14). The grooves (18) are separated from the source/drain diffusion regions (14), thereby increasing the effective channel length to maintain a constant channel length for charge accumulation while enabling the manufacture of smaller memory cells. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: July 12, 2011
    Assignee: Spansion LLC
    Inventor: Masahiko Higashi
  • Publication number: 20110156127
    Abstract: A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated.
    Type: Application
    Filed: October 26, 2010
    Publication date: June 30, 2011
    Inventors: Naofumi TAKAHATA, Masahiko HIGASHI, Yukihiro UTSUNO
  • Patent number: 7943982
    Abstract: There are provided a semiconductor device and a fabrication method therefor including an ONO film (18) formed on a semiconductor substrate (10), a word line (24) formed on the ONO film (18), a bit line (20) formed in the semiconductor substrate (10), and a conductive layer (32) that is in contact with the bit line (20), runs in a length direction of the bit line (20), and includes a polysilicon layer or a metal layer. In accordance with the present invention, a semiconductor device and a fabrication method therefor are provided wherein degradation of the writing and erasing characteristics and degradation of the transistor characteristics such as a junction leakage are suppressed, and the bit line resistance is decreased.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: May 17, 2011
    Assignee: Spansion LLC
    Inventors: Kenichi Fujii, Masahiko Higashi
  • Patent number: 7910980
    Abstract: The present invention provides a semiconductor device and a method for manufacturing thereof. The semiconductor device includes bit lines disposed in a semiconductor substrate, a first ONO disposed between the bit lines on the semiconductor substrate, and a second ONO film disposed on each of the bit lines. The film thickness of a first silicon nitride film in the first ONO film is larger than the film thickness of a second silicon nitride film in the second ONO film.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: March 22, 2011
    Assignee: Spansion LLC
    Inventors: Hiroshi Murai, Masahiko Higashi
  • Publication number: 20100330794
    Abstract: There is provided a method for cleaning a semiconductor device capable of making compatible the inhibition of dissolution of a gate metal material and the acquisition of a favorable contact resistance.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 30, 2010
    Inventors: Hirokazu KURISU, Yutaka Takeshima, Itaru Kanno, Masahiko Higashi, Yusaku Hirota
  • Patent number: 7820547
    Abstract: A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: October 26, 2010
    Assignee: Spansion LLC
    Inventors: Naofumi Takahata, Masahiko Higashi, Yukihiro Utsuno
  • Publication number: 20100151348
    Abstract: There are provided a fuel cell capable of preventing gas leakage through a gas channel, and a method for manufacturing a fuel cell that allows production of such a fuel cell in high volume with lower costs while preventing cracking at corners of the gas channel. In a fuel cell, on a support substrate (1) having a gas channel (10) formed inside are laminated a first electrode (2), a solid electrolyte (3), and a second electrode (4) one after another. The support substrate (1) is formed by laminating green tapes containing support substrate material powder and firing the laminate. Fillet portions (S) are formed at corners of the gas channel (10) of the support substrate (1).
    Type: Application
    Filed: September 20, 2006
    Publication date: June 17, 2010
    Applicant: KYOCERA CORPORATION
    Inventors: Masahiko Higashi, Shuushin Inoue