Patents by Inventor Masahiro Sugimoto

Masahiro Sugimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240072636
    Abstract: Provided is a power conversion circuit, including: a first switching element and a second switching element connected in parallel to each other; and a control unit configured to control turn-on/off of each of the switching elements, wherein a current value at a cross point of current-voltage characteristics when a forward current flows through the first switching element and current-voltage characteristics when a current flows through the second switching element is greater than a rated current value of the power conversion circuit.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 29, 2024
    Inventors: Masahiro SUGIMOTO, Shinpei MATSUDA
  • Publication number: 20240069467
    Abstract: An image forming apparatus includes a first unit including an image bearing member and a second unit. The second unit includes a developing roller to supply the toner to the image bearing member, a mounting portion in which the replenishing container is dismountably mounted and an accommodating portion to accommodate the toner replenished from the replenishing container. The second unit is movable between a first position where the developing roller contacts the image bearing member and a second position where the developing roller separates from the image bearing member. When a moving direction in which the second unit moves from the first position toward the second position is defined as a separating direction, the second unit is urged in the separating direction by a force which the mounting portion receives from the replenishing container when the replenishing container is mounted to the mounting portion.
    Type: Application
    Filed: June 26, 2023
    Publication date: February 29, 2024
    Inventors: Goshi Ozaki, Hiroyuki Munetsugu, Shinichi Nishida, Sohta Sugimoto, Mitsuhiro Sato, Masahiro Suetsugu
  • Publication number: 20240055471
    Abstract: Provided a semiconductor device includes at least: a crystalline oxide semiconductor layer including a channel layer and a drift layer; and a gate electrode arranged over the channel layer across a gate insulating film, and has a current blocking layer between the channel layer and the drift layer. The semiconductor device is characterized in that the drift layer contains a first crystalline oxide as a major component, the current blocking layer contains a second crystalline oxide as a major component, and the first crystalline oxide and the second crystalline oxide have different compositions.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 15, 2024
    Inventors: Masahiro SUGIMOTO, Shinpei MATSUDA, Yasushi HIGUCHI, Kazuyoshi NORIMATSU
  • Publication number: 20240055510
    Abstract: Provided a semiconductor device includes at least: a crystalline oxide semiconductor layer including a channel layer, a drift layer, and a source region; a gate electrode arranged over the channel layer across a gate insulating film; a current blocking region arranged between the channel layer and the drift layer; and a source electrode provided on the source region. The current blocking region is composed of a high-resistance layer. The source electrode forms a contact with the current blocking region.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 15, 2024
    Inventors: Masahiro SUGIMOTO, Shinpei MATSUDA, Yasushi HIGUCHI, Kazuyoshi NORIMATSU
  • Publication number: 20230377775
    Abstract: A NbTi superconducting multicore wire includes a core portion and a first barrier layer arranged around the core portion and composed of a first copper alloy including at least one element selected from Ni or Mn. A filament assembly arranged around the first barrier layer includes NbTi filament assemblies each including at least seven NbTi filaments, embedded in a matrix of a second copper alloy including at least one element selected from Ni or Mn. A second barrier layer is arranged around the filament assembly and composed of the first copper alloy, and a stabilizing layer arranged around the second barrier layer and composed of metal. The NbTi filaments are arranged in circular shapes each having a different diameter, centering on one NbTi filament, and NbTi filaments arranged in a circular shape in an outermost circle being arranged at approximately equal intervals along a circumferential direction.
    Type: Application
    Filed: September 29, 2021
    Publication date: November 23, 2023
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Masahiro SUGIMOTO, Kota KATAYAMA, Hideki II, Tomoya KATO
  • Publication number: 20230298440
    Abstract: A claw gaming machine may comprise a cabinet, a claw assembly, prize objects, and a shooter unit. The machine may be configured to: determine an outcome of a claw game; allow an input device to control the claw assembly; end the claw game when the claw assembly does not pick up a prize object and the determined outcome is a losing outcome; cause the claw assembly to move and release the picked-up object away from the shooter unit when the claw assembly does pick-up a prize object and the determined outcome is a losing outcome, cause the claw assembly to drop the picked-up object on the shooter unit when the claw assembly picks-up the object and the determined outcome is a winning outcome; and cause a winning game presentation display when the claw assembly does not pick up a prize object and the determined outcome is a winning outcome.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 21, 2023
    Inventors: Takaki NARITA, Kenji ENOKIDO, Hiroki SAITO, Satoshi JOKO, Go MIYAMOTO, Akira SHIMIZU, Hiromu SAIGUSA, Jyunichi MURAKAMI, Satoshi NAKATA, Masahiro SUGIMOTO
  • Publication number: 20230290832
    Abstract: Provided is a semiconductor device, including: a gate electrode having at least a part buried in a semiconductor layer; a deep p layer having at least a part buried in the semiconductor layer to a same depth as a buried lower end portion of the gate electrode or a position deeper than the buried lower end portion; and a channel layer, wherein: the deep p layer is formed by a crystalline oxide semiconductor; and a carrier concentration of the deep p layer is higher than a carrier concentration of the channel layer.
    Type: Application
    Filed: April 11, 2023
    Publication date: September 14, 2023
    Inventors: Yasushi HIGUCHI, Masahiro SUGIMOTO, Takashi SHINOHE, Isao TAKAHASHI, Hideo MATSUKI, Fusao HIROSE
  • Patent number: 11727765
    Abstract: A claw gaming machine may comprise a cabinet, a claw assembly, prize objects, and a shooter unit. The machine may be configured to: determine an outcome of a claw game; allow an input device to control the claw assembly; end the claw game when the claw assembly does not pick up a prize object and the determined outcome is a losing outcome; cause the claw assembly to move and release the picked-up object away from the shooter unit when the claw assembly does pick-up a prize object and the determined outcome is a losing outcome, cause the claw assembly to drop the picked-up object on the shooter unit when the claw assembly picks-up the object and the determined outcome is a winning outcome; and cause a winning game presentation display when the claw assembly does not pick up a prize object and the determined outcome is a winning outcome.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: August 15, 2023
    Assignee: ARUZE GAMING AMERICA, INC.
    Inventors: Takaki Narita, Kenji Enokido, Hiroki Saito, Satoshi Joko, Go Miyamoto, Akira Shimizu, Hiromu Saigusa, Jyunichi Murakami, Satoshi Nakata, Masahiro Sugimoto
  • Patent number: 11670688
    Abstract: The disclosure provides a semiconductor apparatus capable of keeping a semiconductor characteristics and realizing excellent semiconductor properties even when using an n type semiconductor (gallium oxide, for example) having a low loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC. A semiconductor apparatus includes a gate electrode and a channel layer formed of a channel directly or through other layers on a side wall of the gate electrode, and wherein a portion of or whole the channel layer may be a p type oxide semiconductor (iridium oxide, for example).
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: June 6, 2023
    Assignee: FLOSFIA INC.
    Inventors: Tokiyoshi Matsuda, Masahiro Sugimoto, Takashi Shinohe
  • Patent number: 11637198
    Abstract: A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: April 25, 2023
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Yasuhiro Ebihara, Masahiro Sugimoto, Yusuke Yamashita
  • Patent number: 11594601
    Abstract: A semiconductor apparatus capable of reducing the leakage current in the reverse direction, and keeping characteristics thereof, even when using n type semiconductor (gallium oxide, for example) or the like having a low-loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC is provided. A semiconductor apparatus includes a crystalline oxide semiconductor having a corundum structure as a main component, and an electric field shield layer and a gate electrode that are respectively laminated directly or through other layers on the n type semiconductor layer, wherein the electric field shield layer includes a p type oxide semiconductor, and is embedded in the n type semiconductor layer deeper than the gate electrode.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: February 28, 2023
    Assignee: FLOSFIA INC.
    Inventors: Tokiyoshi Matsuda, Masahiro Sugimoto, Takashi Shinohe
  • Publication number: 20230016999
    Abstract: A precursor for Nb3Sn single-core superconducting wire includes a Sn-based wire rod, a first Cu-based tube covering an outer circumferential surface of the Sn-based wire rod, an Nb-based tube covering an outer surface of the first Cu-based tube, and a second Cu-based tube covering an outer surface of the Nb-based tube. The Sn-based wire rod contains a matrix phase and at least one kind of hard phases that is harder than the matrix phase. In a cross section parallel to a longitudinal direction of the precursor for Nb3Sn single-core superconducting wire, a maximum dimension of the hard phases in a width direction perpendicular to the longitudinal direction is 50% or less of a minimum dimension in the width direction of the Sn-based wire rod and/or is equal to or smaller than a minimum thickness in the width direction of the Nb-based tube.
    Type: Application
    Filed: December 4, 2020
    Publication date: January 19, 2023
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Daisuke ASAMI, Kota KATAYAMA, Masahiro SUGIMOTO, Hideki II, Hisaki SAKAMOTO, Tomoya KATO
  • Publication number: 20220406504
    Abstract: The superconducting coil includes: a winding frame; and at least two superconducting rectangular wire layers provided in such a manner that a superconducting rectangular wire is spirally wound on an outer surface of the frame such that wires adjacent to each other in an axial direction of the frame are arranged side by side and separated, the wire including an NbTi-based or Nb3Sn-based wire having a surface coated with copper or copper alloy, in which at least a thermoplastic fusible resin is provided in a separated section between the adjacent wires, and when viewed in a cross section including an axis of the frame, at least one of voids that are partitionable on outer surfaces of a total of three wires and a total of four wires located on the two adjacent layers and adjacent to each other are 4% or less in terms of a void ratio (V1).
    Type: Application
    Filed: November 18, 2020
    Publication date: December 22, 2022
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yonghoon KIM, Hideki II, Takumi SATO, Daisuke ASAMI, Masahiro SUGIMOTO, Hirokazu TSUBOUCHI
  • Patent number: 11495695
    Abstract: A semiconductor device with enhanced semiconductor characteristics that is useful for power devices. A semiconductor device, including: an n-type semiconductor layer; an electrode; two or more p-type semiconductors provided between the n-type semiconductor layer and the electrode, the n-type semiconductor layer containing a corundum-structured crystallin oxide semiconductor as a major component, a number of the two or more p-type semiconductor that is equal to or more than three, and the two or more p-type semiconductors that are embedded in the n-type semiconductor layer.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: November 8, 2022
    Assignee: FLOSFIA INC.
    Inventors: Masahiro Sugimoto, Isao Takahashi, Takashi Shinohe, Koji Amazutsumi
  • Patent number: 11450774
    Abstract: A semiconductor device with an enhanced semiconductor characteristics that is useful for power devices. A semiconductor device including: a semiconductor region; a barrier electrode arranged on the semiconductor region; and two or more adjustment regions of barrier height that are on a surface of the semiconductor region and arranged between the semiconductor region and the barrier electrode, the adjustment regions are configured such that barrier height at an interface between the adjustment regions and the barrier electrode is higher than barrier height at an interface between the semiconductor region and the barrier electrode.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: September 20, 2022
    Assignee: FLOSFIA INC.
    Inventors: Masahiro Sugimoto, Isao Takahashi, Hitoshi Kambara, Takashi Shinohe, Toshimi Hitora
  • Publication number: 20220293740
    Abstract: Provided is a semiconductor device comprising at least, a high-resistance oxide film, which is placed in a direction in which a current flows, the high-resistance oxide film having a resistance of 1.0×106 ?·cm or higher. A semiconductor device comprising at least, a gate electrode; a source electrode; a drain electrode; and a high-resistance oxide film, which is placed between the source electrode and the drain electrode and has a resistance of 1.0×106 ?·cm or higher. A semiconductor device comprising at least, a gate electrode; a source electrode; a drain electrode; a high-resistance oxide film; and a substrate with the high-resistance oxide film being placed between the source electrode or/and the drain electrode and the substrate and having a resistance of 1.0×106 ?·cm or higher.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 15, 2022
    Inventors: Masahiro SUGIMOTO, Yasushi HIGUCHI
  • Publication number: 20220285543
    Abstract: There is provided a semiconductor device comprising at least, a crystalline oxide semiconductor layer which has a band gap of 4.5 eV or more; and a field-effect mobility of 10 cm2V·s or higher.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: Masahiro SUGIMOTO, Yasushi HIGUCHI
  • Publication number: 20220285557
    Abstract: A semiconductor device including at least a crystalline oxide semiconductor layer, which has a band gap of 3 eV or more and a field-effect mobility of 30 cm2/V·s or higher.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: Masahiro SUGIMOTO, Yasushi HIGUCHI
  • Publication number: 20220230777
    Abstract: A resin coated superconducting wire includes a matrix resin including a synthetic resin material, and a superconducting wire in the matrix resin. In a transverse cross section of the resin coated superconducting wire, a cross section area of the matrix resin is equal to or larger than the cross section area of the superconducting wire.
    Type: Application
    Filed: May 29, 2020
    Publication date: July 21, 2022
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Hiroyuki FUKUSHIMA, Yonghoon KIM, Hideki II, Takumi SATO, Hirokazu TSUBOUCHI, Masahiro SUGIMOTO
  • Publication number: 20220115168
    Abstract: The present invention provides: a compound superconducting twisted wire in which non-adhesiveness between compound superconducting strands or separation easiness after adhesion is improved while a strength against tension is improved to a degree to be equivalent to or stronger than that of a conventional compound superconducting twisted wire; and a rewinding method thereof.
    Type: Application
    Filed: September 20, 2019
    Publication date: April 14, 2022
    Applicants: FURUKAWA ELECTRIC CO., LTD., TOHOKU UNIVERSITY, TOKAI UNIVERSITY EDUCATIONAL SYSTEM
    Inventors: Masahiro SUGIMOTO, Hirokazu TSUBOUCHI, Daisuke ASAMI, Hideki II, Satoshi AWAJI, Hidetoshi OGURO