Patents by Inventor Masahiro Sugimoto

Masahiro Sugimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220285557
    Abstract: A semiconductor device including at least a crystalline oxide semiconductor layer, which has a band gap of 3 eV or more and a field-effect mobility of 30 cm2/V·s or higher.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: Masahiro SUGIMOTO, Yasushi HIGUCHI
  • Publication number: 20220230777
    Abstract: A resin coated superconducting wire includes a matrix resin including a synthetic resin material, and a superconducting wire in the matrix resin. In a transverse cross section of the resin coated superconducting wire, a cross section area of the matrix resin is equal to or larger than the cross section area of the superconducting wire.
    Type: Application
    Filed: May 29, 2020
    Publication date: July 21, 2022
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Hiroyuki FUKUSHIMA, Yonghoon KIM, Hideki II, Takumi SATO, Hirokazu TSUBOUCHI, Masahiro SUGIMOTO
  • Publication number: 20220115168
    Abstract: The present invention provides: a compound superconducting twisted wire in which non-adhesiveness between compound superconducting strands or separation easiness after adhesion is improved while a strength against tension is improved to a degree to be equivalent to or stronger than that of a conventional compound superconducting twisted wire; and a rewinding method thereof.
    Type: Application
    Filed: September 20, 2019
    Publication date: April 14, 2022
    Applicants: FURUKAWA ELECTRIC CO., LTD., TOHOKU UNIVERSITY, TOKAI UNIVERSITY EDUCATIONAL SYSTEM
    Inventors: Masahiro SUGIMOTO, Hirokazu TSUBOUCHI, Daisuke ASAMI, Hideki II, Satoshi AWAJI, Hidetoshi OGURO
  • Publication number: 20220068091
    Abstract: A claw gaming machine may comprise a cabinet, a claw assembly, prize objects, and a shooter unit. The machine may be configured to: determine an outcome of a claw game; allow an input device to control the claw assembly; end the claw game when the claw assembly does not pick up a prize object and the determined outcome is a losing outcome; cause the claw assembly to move and release the picked-up object away from the shooter unit when the claw assembly does pick-up a prize object and the determined outcome is a losing outcome, cause the claw assembly to drop the picked-up object on the shooter unit when the claw assembly picks-up the object and the determined outcome is a winning outcome; and cause a winning game presentation display when the claw assembly does not pick up a prize object and the determined outcome is a winning outcome.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 3, 2022
    Inventors: Takaki NARITA, Kenji ENOKIDO, Hiroki SAITO, Satoshi JOKO, Go MIYAMOTO, Akira SHIMIZU, Hiromu SAIGUSA, Jyunichi MURAKAMI, Satoshi NAKATA, Masahiro SUGIMOTO
  • Publication number: 20220045211
    Abstract: A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.
    Type: Application
    Filed: October 26, 2021
    Publication date: February 10, 2022
    Inventors: Yuichi TAKEUCHI, Yasuhiro EBIHARA, Masahiro SUGIMOTO, Yusuke YAMASHITA
  • Publication number: 20220005632
    Abstract: An insulation-coated compound superconducting wire includes a compound superconducting wire having a compound superconducting part which includes a first matrix and a plurality of compound superconducting filaments containing compound superconducting phases, a reinforcing part disposed on the outer circumferential side of the compound superconducting part and includes a plurality of reinforced filaments, a second matrix and a second stabilizing material. A stabilizing part is disposed on at least one side among the inner circumferential side and the outer circumferential side of the reinforcing part. An electrical insulation part covers the outer circumferential surface of the compound superconducting wire, in which the insulation-coated compound superconducting wire has a critical current value (Ic) larger than that of the compound superconducting wire before being covered with the electrical insulation part.
    Type: Application
    Filed: September 20, 2019
    Publication date: January 6, 2022
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Masahiro SUGIMOTO, Hirokazu TSUBOUCHI, Kota KATAYAMA, Hideki II
  • Patent number: 11201239
    Abstract: A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: December 14, 2021
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Yasuhiro Ebihara, Masahiro Sugimoto, Yusuke Yamashita
  • Publication number: 20210328062
    Abstract: A semiconductor device including at least one inversion channel region includes an oxide semiconductor film containing a crystal that has a corundum structure at the inversion channel region.
    Type: Application
    Filed: July 11, 2019
    Publication date: October 21, 2021
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE
  • Publication number: 20210328026
    Abstract: A layered structure includes an oxide semiconductor film containing as a major component gallium oxide or a mixed crystal thereof, and an oxide film containing at least one element selected from elements of Group 15 in the periodic table and arranged on the oxide semiconductor film.
    Type: Application
    Filed: July 11, 2019
    Publication date: October 21, 2021
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE
  • Patent number: 11152472
    Abstract: A crystalline oxide semiconductor with excellent crystalline qualities that is useful for semiconductors requiring heat dissipation is provided. A crystalline oxide semiconductor including a first crystal axis, a second crystal axis, a first side, and a second side that is shorter than the first side, a linear thermal expansion coefficient of the first crystal axis is smaller than a linear thermal expansion coefficient of the second crystal axis, a direction of the first side is parallel and/or substantially parallel to a direction of the first crystal axis, and a direction of the second side is parallel and/or substantially parallel to a direction of the second crystal axis.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 19, 2021
    Assignees: FLOSFIA INC., DENSO CORPORATION
    Inventors: Isao Takahashi, Tatsuya Toriyama, Masahiro Sugimoto, Takashi Shinohe, Hideyuki Uehigashi, Junji Ohara, Fusao Hirose, Hideo Matsuki
  • Publication number: 20210320176
    Abstract: A semiconductor device with enhanced semiconductor characteristics that is useful for power devices. A semiconductor device, including: an n-type semiconductor layer; an electrode; two or more p-type semiconductors that is provided between the n-type semiconductor layer and the electrode, the n-type semiconductor layer containing gallium, a number of the two or more p-type semiconductors that is equal to or more than three, and the two or more p-type semiconductors that are embedded in the n-type semiconductor layer.
    Type: Application
    Filed: July 10, 2019
    Publication date: October 14, 2021
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE, Koji AMAZUTSUMI
  • Publication number: 20210320179
    Abstract: A semiconductor device with enhanced semiconductor characteristics that is useful for power devices. A semiconductor device, including: an n-type semiconductor layer; one or more p-type semiconductors; an electrode, the one or more p-type semiconductors that are provided between the n-type semiconductor layer and the electrode, and at least a part of the one or more p-type semiconductors is protruded in the electrode.
    Type: Application
    Filed: July 10, 2019
    Publication date: October 14, 2021
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE, Koji AMAZUTSUMI
  • Publication number: 20210296511
    Abstract: A semiconductor device with enhanced semiconductor characteristics that is useful for power devices. A semiconductor device, including: an n-type semiconductor layer; an electrode; two or more p-type semiconductors provided between the n-type semiconductor layer and the electrode, the n-type semiconductor layer containing a corundum-structured crystallin oxide semiconductor as a major component, a number of the two or more p-type semiconductor that is equal to or more than three, and the two or more p-type semiconductors that are embedded in the n-type semiconductor layer.
    Type: Application
    Filed: July 10, 2019
    Publication date: September 23, 2021
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE, Koji AMAZUTSUMI
  • Patent number: 11072177
    Abstract: A liquid absorbing apparatus for absorbing a liquid component from an ink image formed on a transfer member before transferring the ink image to a print medium includes a liquid absorbing member configured to absorb the liquid component, a support unit configured to support the liquid absorbing member to be movable cyclically, and at least one recovery unit arranged in a moving path of the liquid absorbing member and configured to recover liquid absorption performance of the liquid absorbing member.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: July 27, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahiro Sugimoto, Yuichiro Yanagi
  • Patent number: 10944015
    Abstract: In a first aspect of a present inventive subject matter, a semiconductor device includes an n-type semiconductor layer including a first semiconductor as a major component, an i-type semiconductor layer including a second semiconductor as a major component and a p-type semiconductor layer including a third semiconductor as a major component. The second semiconductor contains a corundum-structured oxide semiconductor.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: March 9, 2021
    Assignee: FLOSFIA INC.
    Inventors: Masahiro Sugimoto, Isao Takahashi, Takashi Shinohe, Toshimi Hitora
  • Patent number: 10943981
    Abstract: In a first aspect of a present inventive subject matter, a semiconductor device includes an n-type semiconductor layer, an i-type semiconductor layer and a p-type semiconductor layer. The i-type semiconductor layer includes an oxide semiconductor as a major component. The oxide semiconductor that is included as the major component of the i-type semiconductor layer includes at least one metal selected from among aluminum, indium, and gallium.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: March 9, 2021
    Assignee: FLOSFIA INC.
    Inventors: Masahiro Sugimoto, Isao Takahashi, Takashi Shinohe, Toshimi Hitora
  • Publication number: 20210013311
    Abstract: A semiconductor device including at least an inversion channel region includes an oxide semiconductor film containing a crystal that contains at least gallium oxide at the inversion channel region.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 14, 2021
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE
  • Publication number: 20200403070
    Abstract: A semiconductor apparatus capable of reducing the leakage current in the reverse direction, and keeping characteristics thereof, even when using n type semiconductor (gallium oxide, for example) or the like having a low-loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC is provided. A semiconductor apparatus includes a crystalline oxide semiconductor having a corundum structure as a main component, and an electric field shield layer and a gate electrode that are respectively laminated directly or through other layers on the n type semiconductor layer, wherein the electric field shield layer includes a p type oxide semiconductor, and is embedded in the n type semiconductor layer deeper than the gate electrode.
    Type: Application
    Filed: November 15, 2018
    Publication date: December 24, 2020
    Applicant: FLOSFIA INC.
    Inventors: Tokiyoshi MATSUDA, Masahiro SUGIMOTO, Takashi SHINOHE
  • Publication number: 20200395450
    Abstract: The disclosure provides a semiconductor apparatus capable of keeping a semiconductor characteristics and realizing excellent semiconductor properties even when using an n type semiconductor (gallium oxide, for example) having a low loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC. A semiconductor apparatus includes a gate electrode and a channel layer formed of a channel directly or through other layers on a side wall of the gate electrode, and wherein a portion of or whole the channel layer may be a p type oxide semiconductor (iridium oxide, for example).
    Type: Application
    Filed: November 15, 2018
    Publication date: December 17, 2020
    Inventors: Tokiyoshi MATSUDA, Masahiro SUGIMOTO, Takashi SHINOHE
  • Publication number: 20200388684
    Abstract: A semiconductor device includes an oxide semiconductor film having a corundum structure or containing as a major component gallium oxide or a mixed crystal of gallium oxide, and the semiconductor device is a normally-off semiconductor device with a threshold voltage that is 3V or more.
    Type: Application
    Filed: July 11, 2019
    Publication date: December 10, 2020
    Applicant: FLOSFIA INC.
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE